FrogWeapons
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How can you re-initialize a program memory for a NIOS II ?
I have an issue which I am trying to debug where I suspect my program memory is being overwritten... The program and data memory is a shared altera_avalon_onchip_memory2. Hitting the reset to the memory and the NIOS (from an external source) when the NIOS is running correctly seems to crash the processor. Should resetting the NIOS and the memory re-initialize the contents ? Thanks.938Views0likes2CommentsRe: Nios II dying after a few minutes running randomly
Hi BB, the information I can give is: - Arria V - Quartus 16.1 - Using internal block RAM only for NIOS. - Just as standard "Altera USB-Blaster" - although probably not too relevant as the failure event happens when connected or not connected ! We have a watchdog in the system, but disabling this has no effect - I also tried forcing an infinite loop to see it the watchdog was causing trouble. Whatever is killing the NIOS seems to be killing the "jtag debug module" - see attached image "Nios lock" Thanks.2.3KViews0likes1CommentNios II dying after a few minutes running randomly
I have a design and randomly the Nios II is dying. --- Details--- - There is a system "heartbeat" counter which is an indication the Nios has stopped - when it does stop, it stops at the same time after reset (power on reset or JTAG reprogram) at about 4 minutes +/- 100ms. -The Nios is dead; when the fail event has happened I can no longer connect to the Nios through JTAG. A reset is needed to reconnect. - The surrounding FPGA logic is still functioning. Some of the peripherals I can still see functioning and I can view signals through signal tap when the Nios is dead. -It happens randomly, most "sessions" go without issue. ---- Things I know --- - It is not power supply related as far as I can tell; it happens both from power on reset and JTAG load reset. -The clocks and reset to the Nios look normal when its dead ( I can view them in signalTap). Can anyone recommend other things to explore ? Thanks !2.3KViews0likes5CommentsArria V CRAM CRC read
In the past on Cyclone III devices I have managed to read the CRAM CRC using the cycloneiii_crcblock. I now need a way to read the CRAM CRC from a Arria V device - "live" from the FPGA. It seems that the arriav_crcblock outputs data from its "Error Message Register" rather than the CRC. Is my understanding correct, if so how do I get the CRAM CRC live from an Arria V ? Thanks.606Views0likes1CommentRe: Using "remote" configuration mode in "standard" configured FPGA
Hi @YuanLi_S_Intel My question was more: what would happen if you enabled the "remote" configuration and had an Intel Remote Update in your design, but did not necessarily intend to use it to update an application. Is there any downside to having it there? Thanks.1.5KViews0likes0CommentsUsing "remote" configuration mode in "standard" configured FPGA
I have a design which is updated remotely using the Altera Remote Update module. To make this function correctly I need to set Assignments->Device->Device and Pin Options->Configuration Mode to "remote". Would there be any problem with using this bitstream in standard mode ? Put another way, if the remote option is set does the FPGA expect something in order to function correctly or will it operate normally. Thanks in advance.Solved1.5KViews0likes3CommentsUsing "remote" configuration mode in "standard" configured FPGA
I have a design which is updated remotely using the Altera Remote Update module. To make this function correctly I need to set Assignments->Device->Device and Pin Options->Configuration Mode to "remote". Would there be any problem with using this bitstream in standard mode ? Put another way, if the remote option is set does the FPGA expect something in order to function correctly or will it operate normally. Thanks in advance.519Views0likes1CommentArria V remote update - watchdog
While in factory configuration can I use the remote update watchdog as a watchdog? I set: IOWR(REMOTE_UPDATE_0_BASE, 0x1, 0x131); //Set wachedog time. IOWR(REMOTE_UPDATE_0_BASE, 0x2, 1); //Enable watchdog. The clock is 20MHz. It never seems to trip. Is it because it is designed to reset to factory config if an application config fails and will never trip while in factory config? Thanks.Solved842Views0likes1CommentReading flash memory contents for comparison
Is there a way to read back an EPCQ128 memory contents in the Quartus Prime Programmer tool that puts the output data in a format that is easily readable? Hex for example. I am aware that I can read back .jic files with the examine function but I know no way of comparing these effectively. For reference, I am trying to debug a RSU that is not yet working and I am trying to work out what is making it into the application page when I do an upload. Thanks.Solved1.2KViews0likes1Comment