Yi
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Re: TSE and Optical Support
Hi Shmuel, Wonder if you are referring to an optical module or external PHY outside the FPGA? actually it depends on the signal that communicates between the FPGA & external PHY, no specific parameter to select but need to select the correct ports and connect them to the target PHY.Re: TSE and Optical Support
Hi, TSE IP supports both MAC level MII/GMII/RGMII interface to PHY or serial interface/SGMII with PMA, so it may use with optical PHY as well, but just notice our TSE IP would have up to 1000Mbps ETH MAC. Enclosed the block diagrams of TSE IP which may help: 1.5. High-Level Block Diagrams (intel.com)Re: ethernet_100g_loopback_off
"TTK failed reading from PHY slave, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset." In most cases, this failure is due to the wrong setting on the reconfig_clk to PHY, which may be the different input pin in .qsf In the compilation design you shared, the reconfig_clk was auto assigned to pin AU15, which should be an clock input of the dev kit. For your design, you'd assign this pin to a 100MHz clock input (if you are not using dev kit), or AR36/AR37 which should be the 100M sysclk input on the dev kit. Also there's chance that clock is correct but reset was pulled, so PHY stuck in the reset mode, this you may also check the reset source or use ISSP to control the reset signal for a try.Re: ethernet_100g_loopback_off
I might find why you failed in board test, after open the .qar file, I found that the design you are using is the compilation test design, under folder: /eth_100g_a10_22_2_0_94_restored/compilation_test_design The compilation design is only for compilation test, which is not set for the board test. To try on board, you can use the design file in folder /hardware_test_design , this should be the ready design that works for target dev kit. Let me know if this works for you, thanks.Re: ethernet_100g_loopback_off
It seems working as the Rx clk and recover clk are both 0Hz, and lock status = 0, though the MAC status looks weird to me either, would suggest to try some debug and see if the loop_off is correctly set or not first. the process is in the *\hwtest\altera\alt_aeu_40\eth_ultra_phy_inc.tcl : proc setphy_lpoff {} { global BASE_RXPHY global ADDR_PHY_PMALOOP # puts "RX PHY Register Access: Setting Serial PMA Loopback\n" reg_write $BASE_RXPHY $ADDR_PHY_PMALOOP 0x0 reg_read $BASE_RXPHY $ADDR_PHY_PMALOOP } May edit the puts here to see if it's set or not first.
