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Vamsi_21's avatar
Vamsi_21
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2 years ago

ethernet_100g_loopback_off

Hi, I have generated a low latency 100g design example by following the guide below: https://www.intel.com/content/www/us/en/docs/programmable/683371/16-1/quick-start-guide.html I tested the s...
Ethernet
Vamsi_21's avatar
Vamsi_21
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi,
I have kept some puts statements in the tcl scripts as you have suggested but for both loopback on and loopback off the rx clk=0 Hz, recover clk=0 Hz, lock status =0 and still it is showing both rx and tx mac stats.

Iam sharing the tcl scripts and also I am attaching the screenshot of the system console window for both loopback on and loopback off.

Yi's avatar
Yi
Icon for New Contributor rankNew Contributor
2 years ago

Weird, Rx clock it not on even when loop is on? Are you able to use toolkit to check the Rx CDR when loopback is on?

  • Vamsi_21's avatar
    Vamsi_21
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi,
    I have taken a signal tap file and added recover clk, reconfig clk to it.

    I set the clock as clk_ref = 644.53125 MHZ
    It was showing recover clk=0 and reconfig clk was running fine.
    Below iam attaching a screenshot of the signal tap window.

  • Vamsi_21's avatar
    Vamsi_21
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi,
    The transceiver toolkit is not launching after loading the design to check Rx CDR when loopback is on.