Unable to checkout 'intelqsimstarter' license
Hello! Good morning from here. I downloaded Quartus Prime Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition and I'm having an issue when trying to run a Unversity Program VWF file. It displays the following error: Failure to obtain a Verilog simulation license. Unable to checkout 'intelqsimstarter' license. I'm trying to use it for academic purpose, that's why I downloaded that version, because I thought it was free. Isn't that simulation included in the free plan? Is there any way to get a free license for that purpose?
Arria10 Transceiver Oversampling
Dear Community, I am trying to set up the MGTs of my Arria 10 GX (10AX115N2F45E1SG) FPGA to send data at a rate of 125 Mbps. This should be the lowest possible rate according to table 3 of the Arria 10 Device Overview. I also found the demo design no. 19 "Arria10 GX SI Board : 11x Oversampling Design using 4 lanes at 150 Mbps using PRBS". Unfortunately, from the slides included in that demo design, I am not sure how to set up my own transceiver. However, I used it as orientation. I set up the respective IP core "Transceiver Native PHY" as TX Simplex with two data channels running at a rate of 1250 Mbps in the standard PCS configuration with an interface width of 10. The fPLL receives a 125 MHz reference clock from an oscillator and creates from that a 625 MHz clock. I use the "tx_clkout" port from the transceiver to clock my own data generator. It has a frequency of 125 MHz. This output is connected to "tx_coreclkin" input. With these settings, the data has a rate of 1250 Mbps, which does not surprise me but leaves me wondering how to achieve the 10x Oversampling? I also tried to clock my data generator with a 12.5 MHz clock, which I created by using an IOPLL that receives its reference from tx_clkout. So I connected the tx_coreclkin port to the 12.5 MHz clock. But again the observed data rate was 1250 Mbps and not the desired 125 Mbps. I hope someone of you can help me. Thank you!
Memory(FPGA) to Memory(HPS SDRAM) data transfer using DMA
Ultimate Goal: I am using a DE1-SoC board, to collect the data from and external ADC and store it in SoC Board. First I am collecting data from ADC to FPGA On-Chip RAM (size10 kB, width 32 BIT ) through SPI and LVDS protocol successfully. Data in FPGA memory is overwritten by the continuous data streaming and ultimatelty transfering and storing full length data in HPS SDRAM. Planned Topology: To store the ADC sampled data for 1 second time, I was trying to transfer the data in chunks (size 5kB) from FPGA On-Chip RAM (size10 kB, width 32 BIT ) to HPS SDRAM (size 1 GB) through "DMA Controller Core" using AXI Bus of 128bit. DMA is controlled by HPS using h2f_axi_master, DMA read_master connected to FPGA On-Chip RAM (Port 1 used by DMA and Port 2 used to store data) and DMA write_master connected to f2h_sdram0_data. Present Testbench: Currently I am focused on collecting 50kb data (32bit width) to HPS SDRAM as 5kB chunks from an 10kB FPGA On-Chip RAM (FPGA On-Chip RAM content is overwritten 5 times) using DMA and AXI Bus. ADC Sampling rate = 1MSPS (1 sample = 32bit width) FPGA Onchip RAM Utilization = 10kB size ( 32bit width, 2560 Address Locations) HPS MPU Frequncy = 925MHZ AXI Clock Frequency = 50MHz AXI Bus width = 128 bit DMA Clock Frequency = 50MHz Expected HPS SDRAM Utilization = 50kB size ( 32bit width, 2560*5 Address locations) Issues: I have writen a code in HPS to collect 10kB data as 5kB chunks in a single loop and made 5 iterations to collect and store 50kB data in SDRAM. When I print the data from the SDRAM, the initial 40kB data is lost and only the last 10kB data is present for the entire 50kB in SDRAM with discontinuties in between and repetition of last 10kB data. Request: Can u please VERIFY/ REVIEW the above process FLOW and guide US ON ADC data collection and storing in HPS SDRAM using DMA. P.S. - Attached HPS C Code, Qsys file, DMA Controller Core Documentation. If possible provide alternative methods / additional ip requirements / example project for the memory(FPGA) to memory(HPS SDRAM) data transfer using DMA for stream data from ADC.
Can't get Quartus Prime Pro Academic License
Everything I do keeps taking me back to the University Program membership form. I'm already accepted and signed in. This is across browsers and devices. No matter what I do, requesting Prime Pro takes me to membership form, trying to open a support request opens the same membership form, trying to get an FPGA Evaluation IP takes me to the same form. I tried resubmitting another redundant form and did get accepted again and the behavior did not change. I cannot do anything without Quartus Prime Pro license as an Academic with an Agilex card.LVDS-Rx IP (DE10 SoC-Cyclone V) interfacing with external ADC : Error in compilation & clock routing
We're using a ALTERA Cyclone V DE10-SoC board and need to interface FPGA “altlvds_rx” IP with an external ADC's LVDS outputs (data, high speed clock, low speed clock). We have tried directly connecting the FPGA pins (LVDS pair) to the “altlvds_rx” IP (Pin: “rx_in”, “rx_inclock”, “rx_enable”) for this purpose. Issues: 1. When I instantiate “altlvds_rx” with Data and clock pins (Pin: “rx_in”, “rx_inclock”, “rx_enable”) as the top module pins, and tried to compile, In Analysis & Synthesis step it showed: • “WRITECLK” and “LOADEN” not properly connected. Request: • How can we correctly interface external ADC’s LVDS signals (data, high speed clock, low speed clock) to “altlvds_rx” via FPGA pins ? • Any peripheral IP should be connected between Top pins (FPGA LVDS pair) and “altlvds_rx” pins (“rx_inclock”, “rx_enable”) to get rid of compilation error and also have successful routing ? • Example designs or suggestions to resolve these errors and successfully interface FPGA “altlvds_rx” IP with external LVDS ADC outputs ? Any guidance would be greatly appreciated.
SALES DETAILS FOR 10M08SCU169C8G
Hi, GOOD Day! This is Pranitha. I am replacement Eng & checking for datasheet, ROHS,CE,& UL Certificates and step file for 10M08SCU169C8G. Currently we are planning to buy that part. Please share quote for 50 qty. Will these certificates available? Please share these Certificates if present ASAP. Thanks, Pranitha.
How do i solve OpenCL Platform?
I've been trying to use oneAPI for over a month, but it always gives this error: OpenCL platform ID is empty OpenCL platform name is empty Failed to find any of these OpenCL platforms: Intel(R) FPGA Emulation Platform for OpenCL(TM) Intel(R) FPGA Emulation Platform for OpenCL(TM) (preview) llvm-foreach: icpx: error: fpga compiler command failed with exit code 14 (use -v to see invocation) make[3]: *** [CMakeFiles/lib.dir/build.make:113: libmyproject-1bb69f05.so] Error 14 make[2]: *** [CMakeFiles/Makefile2:102: CMakeFiles/lib.dir/all] Error 2 make[1]: *** [CMakeFiles/Makefile2:109: CMakeFiles/lib.dir/rule] Error 2 makeup: *** [Makefile:124: lib] Error 2 Traceback (most recent call last): In my research, I discovered that I need the Intel® FPGA Add-on for the Intel® oneAPI Base Toolkit, but I can't find this package anywhere, and when I search on Google, I'm redirected to FPGA Support Package for Intel® oneAPI DPC++/C++ Compiler, I downloaded it, installed it and it always returns the same error, can someone help me! When this is not the error this appears: /home/marcolino/Documentos/python/sample_test/src/firmware/defines.h:4:10: fatal error: 'sycl/ext/intel/ac_types/ac_fixed.hpp' file not found 4 | #include <sycl/ext/intel/ac_types/ac_fixed.hpp> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. make[3]: *** [CMakeFiles/lib.dir/build.make:76: CMakeFiles/lib.dir/src/firmware/myproject.cpp.o] Error 1 make[2]: *** [CMakeFiles/Makefile2:102: CMakeFiles/lib.dir/all] Error 2 make[1]: *** [CMakeFiles/Makefile2:109: CMakeFiles/lib.dir/rule] Error 2 make: *** [Makefile:124: lib] Error 2 Traceback (most recent call last):
