Why is my Cyclone V or Stratix V Altera_PLL reset port is inverted in simulation?
Description Due to a problem in the Quartus® II software version 13.1, you see the the Altera PLL reset port is inverted in gate level simulation. This problem occurs in Cyclone® V or Stratix® V designs when advanced mode or reconfiguration is enabled in the Altera_PLL. Resolution To work around this problem in ModelSim, add the following switch to the vlog command define POSTFIT_SIM_USE_ICD_PLL_MODEL For example add the following lines to the *_run_msim_gate_verilog.do file For Cyclone V designs vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/mentor/cyclonev_*.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/cyclonev_atoms.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL For Stratix V designs vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/mentor/stratixv_*.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/stratixv_atoms.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_primitives.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_lnsim.sv vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/220model.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/sgate.v vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_mf.v vsim -t 1ps transport_int_delays transport_path_delays -voptargs= acc gate_work.<top_level_design.vho/vo> Related Articles Why does the Altera PLL IP signal phase_done not assert in gate-level simulation of dynamic phase shift?
Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteError: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).Why does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Errata - Stratix V and Arria V timing model issues in the Quartus II software version 13.0 SP1
Description Timing models for Stratix® V and Arria® V devices are being updated in the the Quartus® II software version 13.0 SP1 DP5 to address issues in version 13.0 SP1. During timing model finalization of the last 28-nm devices, Altera identified timing model miscorrelations. As part of our continuous improvement processes, Altera audited all devices and found issues affected other devices. Therefore the model changes affect devices that had been designated with "Final" timing status in previous versions of the Quartus II software. Refer to the Workaround/Fix section below to download the software patch that includes the timing model changes, download a script to help determine if your design is affected, and get instructions on how to rerun timing analysis with an updated version of the Quartus II software. Stratix V and Arria V GZ Model Issue: Input Pin to fPLL Reference Clock Path If a design that targets a Stratix V or Arria V GZ device has a fractional PLL (fPLL) reference clock that is fed directly by a dedicated clock input pin, there is a miscorrelation in the input delay. This issue impacts the design behavior only if the design relies on a specified timing relationship between the reference clock input pin and fPLL output. The following timing scenarios are affected: output timing if a destination register feeds off-chip (without the clock also sent off-chip), such as Tco measurement or correction input/receive setup timing for regular or source synchronous inputs clocked by the fPLL timing with zero-delay buffers and external PLL compensation modes Other clocking scenarios, such as the following, are not affected: source synchronous outputs, transceivers, DDR memories sources and destinations that use clocks from same PLL Arria V GX and GT Model Issue: Periphery Routing Mux Paths There are timing miscorrelations related to periphery routing multiplexer paths in Arria V GX and GT devices. The I/O pin-to-core path is missing up to 1 ns delay and the D3 delay chain is not correctly analyzed. This issue affects only general purpose pins feeding the FPGA core directly (with no I/O register). The issue does not affect I/O registers, DDR memory, transceivers or any other paths. Routing between core and the peripheral clock (PCLK) clock buffer is missing ~300ps delay. This issue affects core routing to horizontal and vertical PCLK input, and horizontal PCLK output to core. The issue does not affect I/O pins, transceiver TX/RX, or DPA paths to the PCLK clock buffer. Arria V GX and GT TimeQuest Issue: Clock Polarity Timing into MLAB The TimeQuest Timing Analyzer incorrectly analyzes the timing path in Arria V GX and GT devices when there is mixed polarity of clocks into a MLAB memory block, such as a positive-edge write address register feeding a MLAB memory with a negative-edge write clock signal. TimeQuest analyzes this connection as a full cycle transfer when it should be a half cycle. Resolution Before downloading and installing the new software, you can download the 13_0_sp1_timing.tcl script to see if the design could be affected, as described below. To confirm whether a design is impacted by these timing model issues, retime the design in a patched version of the Quartus II software as described below. If the script or timing analysis with a patched Quartus II software shows timing violations, then you must close timing with the updated Quartus II version. Note that ECO changes may be used in some cases to close timing without a full recompilation. Using the 13_0_sp1_timing.tcl Timing Script: For the Stratix V and Arria V GT issue, the script supports the Quartus II software version 12.1 SP1 DP7 and later. The script reports whether the design\'s timing performance is impacted by the timing model issue. The script generates report panels so that you can view any new failing timing paths in the project\'s Compilation Report, in the TimeQuest Timing Analyzer folder. For the Arria V GT and GZ issues, the script suports the Quartus II software version 13.0 SP1. If the script reports that the design could be affected by the issues, retime the design with the patched Quartus II software to confirm whether the timing performance is impacted. To start the script, run the following command from the command prompt in the project directory for the compiled design: quartus_sh –t 13_0_sp1_timing.tcl -project <project name> [-revision <revision name>] Retiming in the Updated Software Version: To obtain the Quartus II software version 13.0 SP1 DP5 that includes the timing model udpates, refer to the following Solution: How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1? Retime the design with the patched version by following these steps: Back up the design database. Open the design in the current Quartus II software version and export the database. On the Project menu, click Export Database. When you are prompted, export the database to the suggested export_db directory. Start the Quartus II software version with the updated timing model. Open the project in the new version of the Quartus II software. When you are prompted whether to overwrite the older database version, click Yes, and import the database from the export_db directory. Run the TimeQuest Timing Analyzer on the design. Review the timing results. If there are new timing analysis failures, you must close timing with the new timing model. Related Articles Errata - Known Stratix V timing model issues in Quartus II software version 12.1 SP1 Errata - Known Arria V timing model issues in Quartus II software version 12.1 SP1 How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1? Errata – Known Stratix V timing model issues in Quartus II software version 12.1Nios® II Boot from EPCQ or EPCS in Quartus® II 13.1
Description Due to a problem in the Quartus II software, the Quartus Programmer must be used to program EPCQ devices using a generated .jic file in order to enable 4 bytes addressing mode. The nios2-flash-programmer is then required to program the EPCS/EPCQ device with the .flash file generated by the sof2flash tool in order to include the header information required by the new Nios II bootcopier. The new Nios II bootcopier introduced in Quartus® II 13.1 requires a new work flow. Resolution To enable the Nios II processor to load software from EPCS / EPCQ after power cycle or reset in the Quartus II software version 13.1 and later follow the steps below: 1. Add the following 2 lines in your <project>.qsf file. a. set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1" b. set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON 2. Delete the “db”, “incremental_db” and “qsys generated folders” in your project directory. 3. Make sure the Nios II’s Reset Vector is pointing at EPCS/EPCQ Controller. 4. Make sure the Nios II’s Exception Vector is pointing at onchip_memory or some other memory devices. 5. Generate in Qsys. 6. Compile in Quartus II. 7. Note: If the design is not targeting EPCQ device, skip this step Generate the .jic file with “Convert Programming File” tool. a. Select .jic file for “Programming file type”. b. Select the correct EPCQ device for “Configuration device”. c. Make sure “Active Serial” is selected for “Configuring device mode”. d. Click on “Flash Loader”, then click on “Add Device” to select the device you’re using then clicks “Ok”. e. Click on “SOF Data”, and then click on “Add File” to select the .sof file generated by Quartus II compilation. f. Click on the .sof file you have just added, click on “Properties” and enable the “Compression” from there. g. Click on “Generate” to generate the .jic file. h. Program the EPCQ with the .jic file generated with Quartus Programmer and power-cycle the board. 8. Generate the .flash files for the .sof and .elf files with: a. sof2flash --input=hw.sof --output=hw.flash --XX –verbose Note: Replace XX with EPCS for EPCS device and replace XX with EPCQ for EPCQ device b. elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash –verbose 9. Use nios2-configure-sof or Quartus Programmer to configure the FPGA with the .sof file then program the EPCQ device with the Nios II Flash Programmer as follow: a. nios2-flash-programmer --epcs --base=<base address of EPCQ device> hw.flash Note: The EPCQ need to be programmed with the .flash file even if it had been programmed with Quartus Programmer earlier in .jic format b. nios2-flash-programmer --epcs --base=<base address of EPCQ device> sw.flashWhy am I not able to assign a 3.3 V input to a bank with VCCIO connected to 2.5 V
Description The 3.3-V LVTTL and 3.3-V LVCMOS standards support VCCIO connected to 3.3 V, 3.0 V, or 2.5 V for input operation on Arria® V and Stratix® V device families. In versions 11.0 and 11.1 of the Quartus® II software, assigning a pin with a standard that requires VCCIO to be connected to 2.5 V (such as 2.5 V output) and a 3.3-V LVCMOS/LVTTL input will lead to a fitter error. Resolution Make an I/O standard assignment of 2.5 V to inputs that require the 3.3-V LVCMOS/LVTTL standards. The 2.5 V standard input specifications are the same as the 3.3-V specifcations except that Vil is 0.7 V rather than 0.8 V. See the following device datasheets for more information on input voltage thresholds: DC and Switching Characteristics for Stratix V Devices (PDF) Device Datasheet for Arria V Devices (PDF) This problem will be fixed in a future version of the Quartus II software. Related Articles Error (175001) : Could not place pin <pin name>How do I constrain PLL clocks when using clock switchover in 28-nm devices?
Description Due to a problem in the Quartus® II software version 10.1 and later, the derive_pll_clocks command does not correctly constrain all clocks when using Altera_PLL with PLL clock switchover. This problem affects designs targeting Stratix® V, Arria® V or Cyclone® V devices. Instead of creating clocks associated with each input reference clock, derive_pll_clocks only creates clocks for the first reference clock. Resolution To correctly constrain Altera_PLL outputs for each reference clock, use create_generated_clock commands as described in the document below. The document includes instructions for how to create these commands as well as example commands based on the example design below. PLL clock switchover constraints in 28-nm devices (PDF) top_clock_switchover_example_design.qar This problem is scheduled to be fixed in a future release of the Quartus II software. Related Articles Why does my PLL output have an incorrect phase shift in the TimeQuest timing analyzer? Why does derive_pll_clocks fail to automatically constrain PLL output clocks?Why do the signals (nodes) in the Signal Tap Logic Analyzer disappear?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 or earlier, the signals (nodes) initially displayed in the Signal Tap Logic Analyzer might disappear after the trigger occurs. This is because the checkbox in the "Hierarchy Display" GUI window becomes unchecked, causing the signals to be hidden. This problem only occurs when running on Windows* OS. Resolution To work around the problem, manually enable the checkbox in the "Hierarchy Display" GUI window. This problem is fixed beginning with the Quartus® Prime Standard Edition Software version 24.1.
