Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.
Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1 or earlier, you might see this error message when generating PLL IP on Windows* 11 Operating System. The IP generation might complete successfully even though this error message is reported. Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software. The workaround above does not work for the Quartus® Prime Standard Edition Software version 22.1std.2 or earlier. A patch is available to fix this problem for the Quartus® Prime Standard Edition Software version 22.1std.2. The environment variable is still required to prevent the TBBmalloc message from appearing. Download and install patch 2.02 below: Patch 2.02 for Windows (.exe) Readme for patch 2.02 (.txt) This problem is not scheduled to be fixed in the Quartus® Prime Standard Edition Software.Can I use the INPUT_TERMINATION .qsf assignment to assign an on-chip termination (OCT) to Transceiver REFCLK or Transceiver IO pins, in Stratix V, Arria V and Cyclone V devices?
Description No you cannot use the INPUT_TERMINATION assignment to assign an on-chip termination (OCT) to transceiver pins on Stratix® V, Arria® V and Cyclone® V devices. Instead, you must use one of the following qsf assignments : XCVR_GT_IO_PIN_TERMINATION (Stratix V GT transceiver IO pins ony) XCVR_IO_PIN_TERMINATION (transceiver IO pins) XCVR_REFCLK_PIN_TERMINATION (REFCLK pins) Refer to the Altera Transceiver PHY IP Core User Guide (PDF) for more information on how to use these assignments. Note that if you use an INPUT_TERMINATION assignment on the transceiver pins, it will be ignored by the Quartus® II software and the default termination option will be assigned to these pins. Related Articles Error (169033): I/O pin with Termination logic option setting Differential cannot be placed inside I/O Bank because the I/O bank does not support the requested Termination setting.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).How do I instantiate a differential input or output buffer in my design?
Description You can instantiate a differential input or output buffer in your design using the ALTIOBUF Intel® FPGA IP core available in the Intel® Quartus® Prime Software. Resolution The ALTIOBUF Intel® FPGA IP core allows you to specify your input or output pin as a differential receiver or transmitter and then you need to port both the positive and negative signals to I/O pins. This Intel FPGA IP core is supported beginning with the Stratix® III and Cyclone® III device families. For Stratix® II, Cyclone® II, Arria® GX, and previous device families, you cannot instantiate a differential buffer in your design. Instead, use the positive leg of the differential pair in your design, and locate that pin in the Assignment Editor. Give that pin an I/O standard assignment with a value of "LVDS" or the differential I/O standard you wish to use. Refer to the device handbook for a complete listing of the supported I/O standards. The negative leg will automatically be assigned to the corresponding complimentary pin by the fitter when you compile your design. This method is supported for all device families that support differential I/O standards such as LVDS. For more information on the ALTIOBUF Intel FPGA IP core, refer to the ALTIOBUF IP Core User Guide (PDF). Related Articles Internal Error: Sub-system: FIOMGR, File: /quartus/fitter/fiomgr/fiomgr_io_power_region.cpp, Line: 2460How do I successfully perform a lane swap such as the one performed for the QSFP interface of the Intel® Stratix® 10 GX FPGA Development Kit when using the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core?
Description If you are swapping lanes on your PCB for improved signal routing and using the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core, do not also swap the pin assignments of the Intel Stratix 10 device. Instead, leave the original Stratix 10 device pinout and utilize the lane reordering feature supported by the PCS of the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core. The lane reordering feature supported by the of the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core allows the user swap any physical connections as they please without altering the Stratix 10 device pinout. The lane reordering occurs automatically in the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core and no additional register settings are required.Why am I not able to assign a 3.3 V input to a bank with VCCIO connected to 2.5 V
Description The 3.3-V LVTTL and 3.3-V LVCMOS standards support VCCIO connected to 3.3 V, 3.0 V, or 2.5 V for input operation on Arria® V and Stratix® V device families. In versions 11.0 and 11.1 of the Quartus® II software, assigning a pin with a standard that requires VCCIO to be connected to 2.5 V (such as 2.5 V output) and a 3.3-V LVCMOS/LVTTL input will lead to a fitter error. Resolution Make an I/O standard assignment of 2.5 V to inputs that require the 3.3-V LVCMOS/LVTTL standards. The 2.5 V standard input specifications are the same as the 3.3-V specifcations except that Vil is 0.7 V rather than 0.8 V. See the following device datasheets for more information on input voltage thresholds: DC and Switching Characteristics for Stratix V Devices (PDF) Device Datasheet for Arria V Devices (PDF) This problem will be fixed in a future version of the Quartus II software. Related Articles Error (175001) : Could not place pin <pin name>
