Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.
Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).Are there any issues with the UniPHY IP Global Signal assignments seen in the Quartus II software Assignments editor after running the <variation_name>_pin_assignments.tcl script?
Description These assignments which are applied to UniPHY based IP's reset and clock signals are correct and no changes are required by the user. The assignments are shown with Status “?”. This is due to a display issue in Assignments editor and is planned to be fixed in a future version of the Quartus® II software.How do I successfully perform a lane swap such as the one performed for the QSFP interface of the Intel® Stratix® 10 GX FPGA Development Kit when using the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core?
Description If you are swapping lanes on your PCB for improved signal routing and using the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core, do not also swap the pin assignments of the Intel Stratix 10 device. Instead, leave the original Stratix 10 device pinout and utilize the lane reordering feature supported by the PCS of the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core. The lane reordering feature supported by the of the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core allows the user swap any physical connections as they please without altering the Stratix 10 device pinout. The lane reordering occurs automatically in the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core and no additional register settings are required.What is the "minimum pulse width timing specification" of the global reset signal for the UniPHY Controller?
Description Global reset in the UniPHY Controller is connected to PLL areset port. Therefore PLL areset port minimum pulse width (tARESET) for your device will be minimum pulse width timing specification. For example, tARESET for Stratix® IV and Stratix® V devices are 10ns.Why am I not able to assign a 3.3 V input to a bank with VCCIO connected to 2.5 V
Description The 3.3-V LVTTL and 3.3-V LVCMOS standards support VCCIO connected to 3.3 V, 3.0 V, or 2.5 V for input operation on Arria® V and Stratix® V device families. In versions 11.0 and 11.1 of the Quartus® II software, assigning a pin with a standard that requires VCCIO to be connected to 2.5 V (such as 2.5 V output) and a 3.3-V LVCMOS/LVTTL input will lead to a fitter error. Resolution Make an I/O standard assignment of 2.5 V to inputs that require the 3.3-V LVCMOS/LVTTL standards. The 2.5 V standard input specifications are the same as the 3.3-V specifcations except that Vil is 0.7 V rather than 0.8 V. See the following device datasheets for more information on input voltage thresholds: DC and Switching Characteristics for Stratix V Devices (PDF) Device Datasheet for Arria V Devices (PDF) This problem will be fixed in a future version of the Quartus II software. Related Articles Error (175001) : Could not place pin <pin name>Why does the DQS Delay reported in the TimeQuest Timing Analyzer for my altdq_dqs2 based design not match my requested phase shift?
Description Due to a problem in the Quartus® II software versions 13.1 and earlier, you may see an incorrect DQS phase shift reported in the TimeQuest™ Timing Analyzer when the clock used for your DLL is different to the DQS clock rate. The TimeQuest Timing Analyzer incorrectly calculates the phase shift from the DQS clock frequency rather than the DLL clock frequency. Resolution To work around this problem in the Quartus II software version 13.1, apply the following assignment to your quartus settings file (.qsf): set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON This workaround ensures that the requested phase shift is correctly calculated from the DLL clock frequency rather than the DQS clock frequency. This assignment is scheduled to be automatically generated in a future relase of the Quartus II software.
