Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.
Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).Can Altera GX/GT/GZ device high speed transceivers handle Spread Spectrum Clocking (SSC), as required by PCIe or SATA/SAS protocols?
Description Yes, Stratix® and Arria® family GX/GT/GZ transceivers can handle Spread Spectrum Clocking (SSC). You need to make sure that Spread Spectrum Clock device adheres to the modulation frequency (30-33 KHz) and frequency spread (-0.5%) requirements for PCIe and SATA/SAS applications. SATA applications require the rate matching logic to handle a PPM difference from 350 to -5350 PPM, due to SSC downspread. Rate Matcing FIFOs embedded in GX/GT/GZ transceivers cannot handle this high PPM difference. You'll need to implement the rate matching logic in user logic to compensate for this high PPM difference. PCIe specifications require the SSC source to be the same on both systems. Due to common SSC source, there is no PPM difference associated with the spreading at the receiver. Hence, rate matching FIFOs embedded within GX/GT/GZ transceivers can handle the nominal PPM difference of /-300 PPM. ResolutionWhy do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.How to mitigate the security vulnerability in the Nios® II Command Shell utility?
Description Due to a problem in the Quartus ® Prime Standard and Lite Edition Software version 19.1 through 24.1, the Nios® II Command Shell utility included in the Quartus ® Prime Software for Windows* is vulnerable to a Current Working Directory (CWD) planting attack. The Linux* versions are not affected. Resolution To work around this problem, replace the “Nios II Command Shell.bat” Windows Batch File located in the <drive>:\<edition>\<version number>\nios2eds\, with the attached file below. This problem is fixed beginning with the Quartus® Prime Standard and Lite Edition Software version 25.1.Why are tREFI values in simulation and board measurement different from what is set in Altmemphy and UniPHY-based DDR2 SDRAM memory controller?
Description tREFI result in simulation and on the board might be larger than expected if you set tREFI to less than 7.8us in DDR/DDR2/LPDDR2 MegaWizard. DDR/DDR2/LPDDR2 SDRAM IP has a MEM_TREFI parameter, which defines the tREFI parameter in terms of memory clock cycles. Since the minimum value of this parameter is limited to 780, tREFI becomes larger when the memory clock is slower. For example, tREFI for DDR2 SDRAM should be 3.9us at >85C. But if the DDR2 memory clock is 125MHz(8ns), the minimum tREFI value can be 8ns x 780 = 6.24us. tREFI for DDR should be 7.8us. But if the DDR memory clock is 76.9MHz (13ns), the minimum tREFI value can be 13ns x 780 = 10.14us. Resolution As a workaround, if the DDR memory clock is below 100MHz or if you set tREFI to <7.8us on DDR2 memory, you can change the MEM_TREFI parameter in *ddrx_controller_wrapper (Altmemphy-based IP) file or *_c0 (UniPHY-based IP) file to correct the tREFI value. This problem has been fixed in Quartus® II Software Version 12.0.Altera Device Package Information Data Sheet: Known Issues
Description Issue 384162: Altera Device Package Information Data Sheet, Version 16.6 Pin A1 is missing for some of the 484-Pin FineLine Ball-Grid Array (FBGA) - Wire Bond - A:2.40 packages and will be corrected in the next revision. Pin A1 is supposed to be shown but is just missing from the mechanical drawing. Issue 10006628: Altera Device Package Information Data Sheet, Version 16.1 there is an update on thermal resistance value for EP3C16U484, EP3C40U484 and EP3C40F780 devices as Table below: Issue 10006284, Altera Device Package Information Data Sheet version 16.1 The footnote (1) for Table 13. Cyclone III Devices of the Altera Device Package Information Data Sheet is incorrect. The following is the correct footnote: “The E144 package has an exposed ground pad at the bottom of the package. This ground pad is used for electrical connectivity, not for thermal purposes. It must be connected to the ground plane of the PCB.” Issue 10006277, Altera Device Package Information Data Sheet version 16.1 Be informed that there is an update on thermal resistance value for EP3CLS100 and EP3CLS200 as Table 1 below: Issue 10006284, Altera Device Package Information Data Sheet version 16.1 The note for the E144 package under table 13 has changed in this edition of the packaging datasheet and is incorrect. There are not exposed VCC pads under this device, but there is an exposed ground pad. The drawings for the package are correct. Issue 10006283, Altera Device Package Information Data Sheet version 16.1 Table 4 incorrectly states that the EP4SGX290 in the FF35 package is a Single-Piece Lid:FBGA, Flip Chip, Option 2 which points to pages 283-284 of the data sheet. You should use the package outline on pages 303-304 for this device package. Issue 10006120, Altera Device Package Information Data Sheet version 16.1 The package outline top view of 1152-Pin FineLine Ball-Grid Array (FBGA) - Flip Chip - Single-Piece Lid -EP4SGX360 is incorrect. The correct top view should be as Figure 1 (below). The Altera Device Package Information data sheet (PDF) chapter will be updated to show the correct package outline for Stratix IV GX device (1152-Pin FineLine Ball-Grid Array (FBGA) - Flip Chip - Single-Piece Lid - EP4SGX360). Issue 10006119, Altera Device Package Information Data Sheet version 16.1 The POD of 256-Pin FineLine Ball-Grid Array (FBGA), Option 2 – Wire Bond is applicable to F256 packages of Cyclone II, Cyclone III and Cyclone IV products only. The POD of 256-Pin FineLine Ball-Grid Array (FBGA), Option 1 – Wire Bond is applicable to F256 of all products except Cyclone II, Cyclone III and Cyclone IV products, which is assembled in Option 2 package outlines. The Altera Device Package Information Data Sheet will be updated to show the correct package outline for 256-Pin FineLine Ball-Grid Array (FBGA) – Wire Bond. Issue 10006122, Altera Device Package Information Data Sheet version 16.1 The 780-Pin EP4SE230 device should have package description as Channel Lid: FBGA, Flip Chip, Option 1, it is not Dual-Piece Lid: FBGA, Flip Chip, Option 1. The Altera Device Package Information Data Sheet will be updated to show the correct package option for 780-Pin EP4SE230 device. Issue 10006121, Altera Device Package Information Data Sheet version 16.1 The package outline top view of 1517-Pin FineLine Ball-Grid Array (FBGA) - Flip Chip - Dual-Piece Lid - EP4SGX180 is incorrect. The correct top view should be as Figure 1 (below). Resolved Issue 10005898, Altera Device Package Information Data Sheet version 16.0 If you are using an EP4SE820 device it states that the package option you should refer to is Option 4. This is incorrect and you should be referring to Option 3. Refer to the Altera Device Package Information Data Sheet (PDF) version 16.1 for clarification of this issue.How much can I expect the solder balls of a BGA package to shrink after reflow?
Description You can expect the solder balls of a BGA package to shrink by about a third after reflow. For example, if the solder balls have a height of 0.3mm before reflow, they will shrink to a height of about 0.2mm after reflow.
