Why are tREFI values in simulation and board measurement different from what is set in Altmemphy and UniPHY-based DDR2 SDRAM memory controller?
Description tREFI result in simulation and on the board might be larger than expected if you set tREFI to less than 7.8us in DDR/DDR2/LPDDR2 MegaWizard. DDR/DDR2/LPDDR2 SDRAM IP has a MEM_TREFI parameter, which defines the tREFI parameter in terms of memory clock cycles. Since the minimum value of this parameter is limited to 780, tREFI becomes larger when the memory clock is slower. For example, tREFI for DDR2 SDRAM should be 3.9us at >85C. But if the DDR2 memory clock is 125MHz(8ns), the minimum tREFI value can be 8ns x 780 = 6.24us. tREFI for DDR should be 7.8us. But if the DDR memory clock is 76.9MHz (13ns), the minimum tREFI value can be 13ns x 780 = 10.14us. Resolution As a workaround, if the DDR memory clock is below 100MHz or if you set tREFI to <7.8us on DDR2 memory, you can change the MEM_TREFI parameter in *ddrx_controller_wrapper (Altmemphy-based IP) file or *_c0 (UniPHY-based IP) file to correct the tREFI value. This problem has been fixed in Quartus® II Software Version 12.0.
Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteError: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).Why does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Can Altera GX/GT/GZ device high speed transceivers handle Spread Spectrum Clocking (SSC), as required by PCIe or SATA/SAS protocols?
Description Yes, Stratix® and Arria® family GX/GT/GZ transceivers can handle Spread Spectrum Clocking (SSC). You need to make sure that Spread Spectrum Clock device adheres to the modulation frequency (30-33 KHz) and frequency spread (-0.5%) requirements for PCIe and SATA/SAS applications. SATA applications require the rate matching logic to handle a PPM difference from 350 to -5350 PPM, due to SSC downspread. Rate Matcing FIFOs embedded in GX/GT/GZ transceivers cannot handle this high PPM difference. You'll need to implement the rate matching logic in user logic to compensate for this high PPM difference. PCIe specifications require the SSC source to be the same on both systems. Due to common SSC source, there is no PPM difference associated with the spreading at the receiver. Hence, rate matching FIFOs embedded within GX/GT/GZ transceivers can handle the nominal PPM difference of /-300 PPM. ResolutionWhy do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why do the signals (nodes) in the Signal Tap Logic Analyzer disappear?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 or earlier, the signals (nodes) initially displayed in the Signal Tap Logic Analyzer might disappear after the trigger occurs. This is because the checkbox in the "Hierarchy Display" GUI window becomes unchecked, causing the signals to be hidden. This problem only occurs when running on Windows* OS. Resolution To work around the problem, manually enable the checkbox in the "Hierarchy Display" GUI window. This problem is fixed beginning with the Quartus® Prime Standard Edition Software version 24.1.Error: out of memory in module <module name >
Description You may see this error when compiling large designs targeting high density devices using the Quartus® II 32-bit software. Compiling high density designs may consume greater than the 2 to 3 GB of memory resources available per process on 32-bit operating systems. To resolve this issue, use the Quartus II 64-bit software with a 64-bit operating system. Refer to the Quartus II device support release notes (PDF) for the memory requirements of Altera devices. To verify if you are using the Quartus II 64-bit software, on the Help menu click About Quartus II. The window should show "Quartus II 64-Bit Version <number>". If you are using a Windows-based 64-bit operating system, you can switch to the 64-bit software as follows: Launch Quartus II (64-Bit) from its desktop shortcut or the program menu listing If you are using a Linux 64-bit operating system, follow one of these steps to switch to the 64-bit software: Set an environment variable called QUARTUS_64BIT to 1 and launch the Quartus II software setenv QUARTUS_64BIT 1 Launch the Quartus II software with the --64bit command line option: quartus --64bit Related Articles Why do I get an Out of Memory in module Quartus.exe when trying to program a 1GB flash using the Quartus II programmer? Can I allocate more than 2 GB of RAM for the Quartus II software on Windows? How do I enable 64-bit processing in the Quartus II software on Linux workstations?Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
