Error: Error during execution of "{C:/altera/12.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Description You may experience the above error when generating a UniPHY-based memory controller. The error occurs because one of the system environment variables 'TEMP' points to a network drive and not a local drive. Resolution The workaround is to point the TEMP variable to the local machine, such as the C: drive. Also the variable HOMEDRIVE should point to the local machine.Why do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.What is the recommended termination guideline for mem_reset_n when using DDR3 SDRAM controller with UniPHY?
Description Altera® does not recommend terminating the mem_reset_n signal. DDR3 DIMMs typically do not use any termination on the memory reset signal. Refer to the memory vendor datasheet for any memory reset termination guidelines. Resolution Related Articles Can I use a USB Blaster download cable for AES key programming? Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY based controller Can I place bonded transceiver channels non-contiguously in Stratix® V and Arria® GZ transceiver devices?Why is my DDR2 UniPHY controller interface only 50% efficient for back-to-back read or write commands?
Description The High Performance Controller II (HPCII) used by the DDR2 UniPHY and ALTMEMPHY cores issues back to back read/write commands on every other controller clock cycle ( afi_clk ). If you have the burst length set to 4 for a half rate controller, then the controller will only use 50% of the maximum efficiency on the bus. This is an expected behavior of the half rate controller for burst length of 4 implementation. Resolution There are two workarounds: Use a full-rate HPCII controller when you set the burst length to 4. Use a half-rate HPCII controller when you set the burst length to 8.Error : exception in thread java.lang.outOfMemoryError: java heap space
Description You may receive this error message when running System Console, due to the memory requirements of System Console exceeding the maximum heap size allocated to the Java VM. When you launch System Console it runs in a Java VM with a default maximum heap size of 512MB. Resolution To avoid this error, increase the maximum heap size that is allocated to the Java VM by using the -jvm-max-heap-size <heap size> switch when you launch System Console in command line mode. To do this, run the following command: /sopc_builder/bin/system-console -cli --jvm-max-heap-size=<heap size> --jvm-max-heap-size defines the maximum memory size to be used for allocations when running System Console. This value is specified as <size><unit> where unit can be m (or M) for multiples of megabytes or g (or G) for multiples of gigabytes. Related Articles Error: Error writing sopcinfo report java.lang.OutOfMemoryError: Java heap spaceHow do I determine the phase shift and duty cycle for the required clocks if I am using ALTLVDS_RX and ALTLVDS_TX in external PLL mode?
Description You can determine the phase shift and duty cycle for the required clocks when using ALTLVDS_RX and ALTLVDS_TX in external PLL mode by first compiling an example design with ALTLVDS_RX or ALTLVDS_TX using an internal PLL. Use the settings that the Quartus® II software uses to configure the internal PLL in the example design as the settings you enter in the external PLL. To check the PLL settings in the Fitter report, expand the Resource section, and then expand PLL Usage. The report shows the duty cycle, phase shift and clock frequency for each of the required clocks for the ALTLVDS_RX and ALTLVDS_TX interfaces. You can then use these parameters for the external PLL settings in your design. Related Articles How do I implement ALTLVDS in External PLL Mode for Stratix V, Arria V, and Cyclone V devices? How do I implement the ALTLVDS_RX and ALTLVDS_TX megafunctions with External PLL mode in Arria II GX devices? How do you implement the altlvds megafunction with the External PLL option in Stratix III devices?VCS generates this warning when doing a functional simulation of the DDR, DDR2 and DDR3 SDRAM High Performance Controller II IP. This warning appears because the code is connecting a 1-bit LSB of a 4 bit bus to a 2-bit input
Description VCS generates this warning when doing a functional simulation of the DDR, DDR2 and DDR3 SDRAM High Performance Controller II IP. This warning appears because the code is connecting a 1-bit LSB of a 4 bit bus to a 2-bit input, so bit 2 of the clk_reset scan_din input is undriven. The leveled sequencer does not use scan chains on mem_clks and this doesn't matter for a non-levelled design (i.e, DDR2) since it doesn't use the scan chains either. Hence this message can be safely ignored. Warning-[PCWM-W] Port connection width mismatch <path_name>/SdramController_PLL_Master_phy_alt_mem_phy.v, 1395"clk". The following 1-bit expression is connected to 2-bit port "scan_din" of module "SdramController_PLL_Master_phy_alt_mem_phy_clk_reset", instance "clk" Expression: scan_din[0] use lint=PCWM for more detailsDo I need to drive fftpts_in of the FFT Intel® FPGA IP core even if I'm not changing the block size?
Description You may receive source errors (missing SOP, missing EOP) when attempting to process data through the FFT Intel® FPGA IP core when fftpts_in not being driven or being driven incorrectly. Resolution fftpts_in must be driven, even if one is not dynamically changing the block size. For a fixed block size implementation, it should be driven to match the transform length selected in the parameter editor.Error (129036): Output port DATAOUT on atom "<slave DQS signal>", which is a arriav_delay_chain primitive, is not connected to a valid destination
Description This error may occur during synthesis when the afi_reset_n signal of a slave controller is not connected to the master controller's afi_reset_n output. Resolution Connect the afi_reset_n of the slave controller to the master controller\'s afi_reset_n output.