Are Arria® II, Stratix® II, Stratix® III and Stratix® IV devices RoHS and Leaded compliant?
Description Intel has introduced new ordering part number (OPN) suffixes for Arria® II, Stratix® II, Stratix® III and Stratix® IV devices for Restriction of Hazardous Substances (RoHS) and Leaded compliance. The new part numbers will have "N" suffix for RoHS5 devices (applicable to Arria® II, Stratix® II, Stratix® III and Stratix® IV devices), "G" suffix for RoHS6 devices (applicable to Arria® II, Stratix® III and Stratix® IV devices) and "P" suffix for Leaded devices (applicable to Arria® II, Stratix® III and Stratix® IV devices) This additional information can be found in the documents below for each respective device family. Arria® II: Overview for the Arria II Device Family Stratix® II: Reference & Ordering Information Stratix® III: Stratix III Device Family Overview Stratix® IV: Overview for the Stratix IV Device FamilyHow do I calculate the frequency, phase shift and duty cycle for clocking ALTLVDS soft SERDES using external PLL mode?
Description Altera® devices have two types of implementation for SERDES blocks - hard SERDES and soft SERDES (built from logic cells). This document will discuss how to calculate the frequency, phase shift, and duty cycle for each of the clocks needed for the external PLL interface with soft SERDES. By selecting external PLL mode, you must set the PLL parameters, but you can access other features of the PLL such as clock switchover, PLL reconfiguration, and other output clocks which would otherwise not be available when using the internal PLL. Download this How-To document to learn how you can calculate the frequency, phase shift, and duty cycle for each of the clocks used for external PLL mode with soft SERDES. Related Articles Why does TimeQuest not analyze the tx_enable and tx_inclock or rx_enable and rx_inclock timing paths when using the ALTLVDS megafunction in external PLL mode?Are there USB Blaster drivers for Windows 7 if I am using the Quartus II software version 9.1SP2 and earlier?
Description Yes, but you will need to download the USB-Blaster™ drivers that are included with Quartus® II software version 10.0. The Quartus II software versions 9.1SP2 and earlier do not have official support for Windows 7 and the USB-Blaster drivers are unsigned which are not supported by Windows 7. As a work-around you can use drivers from the Quartus II software version 10.0. If you have not downloaded the Quartus II software version 10.0 you can download the drivers below. If you currently have a USB-Blaster installed you will have to go into the Device Manager, and expand the Universal Serial Bus Controllers section, select the Altera® USB-Blaster, and then select Update Driver. A Hardware Update Wizard will appear. You will need to do one of two things: 1) If have Quartus II software version 10.0 installed, you will need to select the (directory path to drivers) 2) Download the USB-Blaster driver and point to the unzipped USB-Blaster folder.Why is the PCI express address incorrect when using the Tx Slave Avalon-MM port on the IP Compiler for PCI Express in QSys?
Description Due to a bug in the IP Compiler for PCI Express® in versions 11.1, 11.1sp1 and 11.1sp2 of the Quartus® II software, addresses may not be translated correctly when using the TX Avalon®-MM slave port to generate PCI Express requests when all bits of ByteEnable are not asserted. For example, if PCI Express requests are generated with only the upper dword enabled on the TX Avalon-MM slave port, the PCI express request that is generated will be a single dword request but with the address of the lower dword. This problem will be fixed in a future version of the Quartus II software. Resolution A patch is available to fix this problem for the Quartus II software version 11.1sp1. Download and install patch 1.16 from the appropriate link below. Quartus II 11.1sp1 Patch 1.16 for Windows Quartus II 11.1sp1 Patch 1.16 for Linux Quartus II 11.1sp1 Patch 1.16 Readme fileWhy do MSI's not work on my altpcie_demo application for the PCI Express Avalon-ST High-Performance Reference Design?
Description Due to a problem with the provided driver information file(.inf), the reference design Device ID does not match that expected by the driver and Message Signal Interrupts (MSIs) are not enabled. This problem causes the kit to be displayed in the Windows® Device Manager under "Other devices" as "PCI Device" with a yellow "!" warning icon next to it. The reference design can be found here: http://www.altera.com/support/refdesigns/ip/interface/ref-pciexpress-hp.html The demo application package is here: https://www.altera.com/support/software/download/refdesigns/ip/interface/dnl-pciexpress-hp.jsp Resolution To correct the device ID and enable MSIs, copy the attached (.inf) and (.bat) files to: <your path>/altpcie_demo/JungoDrivers Then run the (.bat) file as Administrator and restart your PC. Updated Information File Updated Batch File Related Articles Why does my altpcie_demo application display as PCI Device under Other Devices in the Windows Device Manager for the PCI Express Avalon-ST High-Performance Reference Design?Why does my PCI Express end point design, using legacy interrupts, send the "Deassert_INTA" message immediately after the Assert_INTA message, when signal Rxmirq_irq[n] is still asserted?
Description Due to a problem with the PCI Express® core implementation in the Quartus® II software, the Deassert_INTA message may be sent out shortly after the Assert_INTA message, while the Rxmirq_irq[n] signal is still asserted. This is not the intended operation of the legacy interrupt logic. This issue affects designs implemented in Qsys, starting with Quartus II software version 11.0. To workaround this issue: 1. Download the following file:pciexp_dcram.v 2. Copy this file to the following directory in your Quartus II installation directory: <install_dir>/ip/altera/ip_compiler_for_pci_express/lib 3. Regenerate the PCI Express core within Qsys 4. Regenerate the Qsys design 5. Recompile your project This issue will be fixed in a future release of the Quartus II software. Resolution This issue has been fixed in software release v11.1 and laterWhy the DFE cant find the optimal parameters sometimes?
Description Quartus® II 10.0 SP1 sets incorrect parameters for the Decision Feedback Equalizer (DFE) circuitry that could adversely impact the link BER. You can install Quartus II 10.0 SP1 patch 1.144 and recompile your design to resolve this issue. This patch sets the DFE parameters correctly during compilation. If your design uses the DFE feature. Download: Download the version 10.0sp1 patch 1.144 for Windows (.exe) Download the version 10.0sp1 patch 1.144 for Linux (.tar) Download the Readme for the Quartus II software version 10.0sp1 patch 1.144 (.txt)What reset sequence should I follow to fix link training hardware issues in my PCI Express Soft IP Gen2 x4 or x8 design in Stratix IV GX/GT devices?
Description If you are experiencing problems with link training or down training in Stratix® IV devices using the PCI Express Compiler in the Quartus II software version 9.1 and later, targeting the software IP block (SIP) in Gen2 x4 or x8 please ensure that your Reset Controller implements the following sequence. Please refer to the diagram below: Figure 1. PCI Express Reset Sequence Requirement View full size Assert pll_powerdown for pll_powerdown duration (1) to (2) When pll_locked asserts (3), de-assert tx_digitalreset (4) When busy de-asserts (5), de-assert rx_analogreset (6) Wait 75us after se-asserting rx_analogreset (6), then de-assert rx_digitalreset (7) pipephydonestatus de-assertion (8) will indicate that the LTSSM_state is transitioning to detect.active (9) state pipephystatus changing to receiver.detected (10) state will preceed the LTSSM_state transitioning to polling (11) state When the LTSSM_state changes to polling (11) assert rx_digitalreset (12) Monitor the rx_signaldetect[n-1:0] signals until any one of them asserts (13) and stays asserted for 3ms (14) When any rx_signaldetect signal has remained asserted for 3ms (14), de-assert rx_digitalreset (15) The reset sequence of the PCI Express (PIPE) Function Mode is now completed.Why doesn't the Soft IP PCIe* core send my Avalon®-MM memory read request to PCIe* bus?
Description Due to a bug in Soft IP PCIe* generated by SOPC builder, the core may not send memory read request (MRD) to PCIe* bus although it is presented correctly on Avalon®-MM interface. This issue does not affect Soft IP with Avalon®-ST interface or any Hard IP PCIe* cores. If you are using Quartus® II software version 10.1, you can download download and install the following patch to resolve this issue. Download the Download the Quartus II software version 10.1 Patch 0.13 for Windows (.exe) Download the Download the Quartus II software version 10.1 Patch 0.13 for Linux (.tar) Download the Readme for the Quartus II software Download the Quartus II software version 10.1 Patch 0.13 (.txt) Currently there is no workaround for earlier Quartus® II software versions. If using an earlier version of the Quartus® II tools, Intel® recommend moving to Quartus® II version 11.0 software.Is there a known issue with the scandata port when using the ALTPLL_RECONFIG megafunction in the Quartus® II software version 13.1?
Description The scandata output port in the ALTPLL_RECONFIG megafunction has been inverted in the Quartus® II software version 13.1. Resolution This problem is scheduled to be fixed in a future release of the Quartus II software. A patch is available to fix this problem for Quartus II software version 13.1. Download and install patch 0.81 and recompile your design. Quartus II versions earlier than 13.1 are not affected. Download the version 13.1 patch 0.81 for Windows (.exe) Download the version 13.1 patch 0.81 for Linux (.run) Download the Readme for the Quartus II software version 13.1 patch 0.81 (.txt)
