Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.Why is Agilex® 5 and Agilex® 3 FPGA External Memory Interfaces (EMIF) IP missing from the BSP Linker when the Nios® V processor Board Support Package is generated?
Description Due to a problem in the Quartus ® Prime Pro Edition starting since software version 24.1, the Agilex ® 5 and Agilex ® 3 FPGA EMIF IP is missing from the BSP Linker when generating the Board Support Package. This might occur for Nios ® V processor designs targeting Agilex 5 FPGA or Agilex 3 FPGA, that uses EMIF IP. This is because Agilex 5 and Agilex 3 FPGA EMIF IP are missing the isMemoryDevice agent information. Refer to Nios® V Processor Software Developer Handbook - Memory-Mapped Slave Information (PDF) for information about isMemoryDevice agent information. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 5 FPGAs and SoCs (PDF) for information Agilex ® 5 FPGA EMIF IP. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 3 FPGAs and SoCs (PDF) for information Agilex ® 3 FPGA EMIF IP. Resolution To work around this problem in the Quartus ® Prime Pro Edition in all the affected software version, apply either one of the following workarounds: Workaround 1: Manually add isMemoryDevice to the EMIF IP (in Platform Designer only) Select the s*_axi4 signal (mainband AXI4 from fabric to controller) that connects to the Nios ® V processor’s instruction/data manager. Right-click, and click Edit Component Instantiation ... Select s*axi4 and edit the Assignments. Enter new Key as embeddedsw.configuration.isMemoryDevice, and Value as 1. Save the new assignment. Generate a new BSP. Workaround 2: Manually define EMIF IP linker memory device Refer to the Nios V Embedded Processor Design Handbook - Defining Address Span Extender Linker Memory Device. The example demonstrates how to manually define Address Span Extender linker memory device. For this problem, apply the same procedure but on the EMIF IP directly. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software. Related Articles LPDDR4 not available in NIOS® V/g linker script - Agilex® 5 FPGA, Quartus® 26.1 Pro Issue with BSP Creation for Nios® V/m Using LPDDR4 on Agilex® 5 FPGA (Quartus® 24.1 & 24.3.1)Why does Board Support Package Editor fail to generate embedded peripheral IP drivers when generating BSP FreeRTOS project for Nios® V processor?
Description Due to a problem in the Quartus ® Prime Standard Edition Software version 24.1 and 25.1, the BSP Editor fails to generate embedded peripheral IP drivers, when it is generating BSP FreeRTOS project for Nios ® V processor. This is because the BSP Editor is not enabled to generate those drivers in FreeRTOS. Refer to Embedded Peripherals IP User Guide - Driver Support for the list of embedded peripherals with driver support. Resolution Patches are available to fix this problem for the Quartus ® Prime Standard Edition Software version 24.1 and 25.1 Linux and Windows versions. Download and install patch below. Quartus® Prime Standard Edition Software v24.1 Patch 0.01 Quartus® Prime Standard Edition Software v25.1 Patch 0.01 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition Software.Why does Nios® V/g processor experiences data corruption when it is enabled with TCM and ECC?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 26.1, data corruption might occur in Nios ® V/g processor designs with tightly coupled memory (TCM) and error correction code (ECC). Both features must be enabled to observe this problem. It is caused by an RTL bug in the processor, which renders failure when the processor executes sw (store word), followed by sh (store halfword) or sb (store byte) instructions. For example, # Initially, value of Y is 0x0001CCCC. li t0, 0x12345678 li t1, 0x200A sw t0, 0(Z) # Store 0x12345678 word into Z sh t1, 0(Y) # Store 0x200A into lower half of Y Result Final value of Y Description Expected 0x0001200A Upper-half of Y is preserved as 0x0001, while lower-half of Y is changed to 0x200A. Actual (Data Corruption) 0x1234200A Upper-half of Y is corrupted to 0x1234, while lower-half of Y is changed to 0x200A. The 0x1234 is from the previous Store Word (sw) instruction. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 26.1, apply either one of the solutions below: Disable TCM. Disable ECC. This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software.Why does Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 turns compiler warnings into errors?
Description In the Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) and later, you might see compilation error related to the following errors: Implicit int types (-Werror=implicit-int) Implicit function declarations (-Werror=implicit-function-declaration) Typos in function prototypes (-Werror=declaration-missing-parameter-type) Incorrect uses of the return statement (-Werror=return-mismatch) Using pointers as integers and vice versa (-Werror=int-conversion) Type checking on pointer types (-Werror=incompatible-pointer-types) This is due to an update in GCC 14 – GNU: Certain warnings are now errors, which affects future GCC versions. For more information, Ashling* RiscFree* IDE for Altera FPGAs software version 25.3.1 (1 st August 2025) is using GCC 13.2. Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) is using GCC 15.2. Thus, Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) and future versions are affected. Note that Ashling* RiscFree* IDE for Altera FPGAs software version 25.4.1 (31 st Oct 2025) is paired with Quartus ® Prime Pro Edition software version 26.1. Resolution GNU recommends resolving all the new errors for better code quality. If necessary, you may refer to the workaround – GNU: Turning errors back into warnings. In Board Support Package Editor, add "-fpermissive" in hal.make.cflags_user_flags.Why does downloading ELF file into Nios® V/g processor fail when disabled branch prediction, while enabled instruction cache?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, downloading ELF file into Nios ® V/g processor might fail when both the conditions below are fulfilled. Branch prediction is disabled, and Instruction cache is enabled The niosv-download command returns the error message below. Unexpected vCont reply in non-stop mode: E30 ERROR: GDB failed. This is because there is an RTL bug in the instruction cache related to its reset state. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 25.3.1, Either enable branch prediction, Or disable instruction cache This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.Why does Ashling* RiscFree* IDE for Altera* FPGA software reports unresolved inclusion warnings, despite a successful build of Nios® V processor software project?
Description Due to a problem in multiple versions of Ashling* RiscFree* IDE for Altera® FPGA, the unresolved inclusion warning might occur for any Nios ® V processor software projects. Note that, the warning is harmless. The affected software project will still build successfully. This is caused by a bug in the Indexer of Ashling* RiscFree* IDE, which fails to search for the relevant project files. The affected Ashling* RiscFree* IDE for Altera FPGA are: Software version v25.1.1 (dated as 31 st Jan 2025) Software version v25.2.1 (dated as 9 th May 2025) Software version v25.3.1 (dated 1 st August 2025) Resolution This problem is currently scheduled to be resolved in future release of Ashling* RiscFree* IDE for Altera FPGA software version v26.1.0 (dated as 19 th Dec 2025). Meanwhile, you may safely ignore this warning, as it does not affect the functionality of your project. If needed, please refer to the related article for the recommended workaround. Related Article: Ahsling RiscFree IDE 25.1.1: Unresolved inclusion | Altera CommunityWhy does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active?
Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages.Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWhy does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).
