Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera
Hi, This is regarding the clock tree used in the Agilex 7 FPGA M-Series Development Kit. I have a few questions and would appreciate your clarification. 1. Why is the 390.625 MHz SyncE clock generated by the Si5518 (U92) provided to the Si5395 (U14) and subsequently routed through the Si5391 devices to the DDR5 and HBM reference clock pins of the Agilex M FPGA? 2. Why is the output of Si5391 (U35) connected to an input of another Si5391 (U93), and similarly, why is an output of U93 connected back to an input of U35? What is the purpose of these interconnections? 3. Why is the 312.5 MHz LVDS SAMPLE clock output from the Si5518 connected to the ToD block of the Agilex M FPGA? What function does this signal serve in the ToD block? 4. In the Si5518, why is the PPS output looped back to one of the PLL inputs (1PPSFB)? What is the purpose of this feedback connection in the schematic? 5. Similar loopback connections are also observed in Bank 13C of the Agilex M FPGA. Why is this loopback connection required ? I would appreciate your response to these queries. Any pointers to relevant documentation or application notes would also be very helpful Regards, Thulasi
LLM Implementation on Agilex 5 E-Series 065B Modular Dev Kit
I am currently working on deploying Large Language Model (LLM) inference using FPGA AI Suite on the Agilex 5 E-Series 065B Modular Development Kit. I have two clear and specific questions: Is the Agilex 5 E-Series 065B officially supported for LLM / Transformer inference with FPGA AI Suite? Is the following workflow officially supported for LLM inference on this board? Step 1: Export a pre-trained LLM from Hugging Face to OpenVINO IR format using optimum-intel Step 2: Generate the target FPGA architecture file using architecture_optimizer for Agilex 5. Step 3: Compile the OpenVINO IR model for the FPGA using: • dla_compiler → for Sequential flow, or • Spatial Compiler → for Spatial flow. Step 4: Integrate the generated FPGA AI Suite IP into a Quartus Prime project, generate the bitstream, and program it onto the Agilex 5 E-Series 065B board. Step 5: Run inference using the FPGA AI Suite runtime (host application). I understand this may not be a push-button process and could require significant modifications to the generated RTL — but is this workflow still considered a viable starting point for implementing LLM / Transformer inference on the Agilex 5 E-Series 065B? Thank you.
Fitter error in A5ED043AB23AI2V Example design
Hi, I have tried using the example design of the A5ED065BB32AE4SR0 development kit and modified the part number to A5ED043AB23AI2V. During compilation, I am encountering a fitter error when both PCIe and USB 3.1 are enabled together. However, I am able to compile successfully when using each interface individually. Could you please help me understand how to resolve this issue?Agilex5 Eagle ES, NIOS-V + TSE IP
Trying to setup a NIOS-V with a TSE MAC to utilize the ethernet interface connected to the FPGA on the Agilex Eagle ES devkit. NIOS executes firmware and able to read the PHY registers. But when connecting the ethernet cable nothing seems to happen, status registers does not change and no link-up is reported. Does anyone know of any examples using the NIOS-V and TSE with RGMII interface that I can look at to troubleshoot the issue ?Arrow AXE5 Eagle Board JTAG issue
Hi, I have an AXE5 eagle board. The Quartus Programmer on Auto-Detect does show the usb blaster3 but the device is named UNKNOWN_364F0DD instead of A5ED065BB32AES4. What do you think could be the issue? BTW I am on Linux RHEL 8. I am using Arrow blaster and used FTProg to flash it as USB Blaster 3 as suggested by guide
Device stopped receiving config data: Internal error (0x0000, 0x00000000, 0x1800).
Using Agilex AGFB014R24A (E-Tile board). .jic flashes successfully, but no UART logs are observed after boot. Observed attached logs attached When programming the corresponding .sof via JTAG, configuration fails at ~86%. Device has stopped receiving configuration data Error message received from device: Internal error. (Subcode 0x0000, Info 0x00000000, Location 0x00001800) Operation failed Ended Programmer operation Looking for clarification on this internal error and recommended workaround.Differential Signal Transmitter on Agilex 5 FPGA Modular Dev Kit
We will use the SOM Module of the Agilex 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1) for a new project with our own designed carrier board. For this design we need multiple differential transmit and receive signals from I/O Bank 2A_B and 2A_T (→ 1.2V bank supply). We started with a basic design to evaluate usable I/O Standards. We have seen that we can use differential receiver with the 1.2V bank supply but it is not possible to use "True Differential Signaling" on transmit pins with 1.2V bank supply. For our purpose it is necessary to generate differential transmit signals correctly working with LVDS inputs on the receiver site. Is there an alternative differential signal output generating a correct LVDS signal for a LVDS receiver working with the 1.2V bank supply (e.g. POD12 with special termination)? What happens when setting differential transmit and receive pins to "1.3V True Differential Signaling" to get Quartus running without an error but physically using only 1.2V bank supply? Will this only decrease signal swing on transmit pins or is this not working? Or could this damage the FPGA transmit and receive pins of the FPGA? The SOM schematic does not show any possibility to disconnect the I/O Banks 2A_B and 2A_T from onboard 1.2V supply to use an alternative external 1.3V supply. Is there the a possibility to supply these banks externally by 1.3V? Which other alternatives do we have to get differential signaling output working?
