yolov3_tiny_tf run_inference_stream problem
i have completed successfully Arria 10 SoC demo project resnet-50-tf on Arria 10 SoC devkit. (my tool version intel fpga ai suite 2025.1 and open vino 2024.6). i have used the precompile arria10 wic image. Arria 10 SoC devkit: https://www.altera.com/products/devkit/a1jui0000049utgmam/arria-10-sx-soc-development-kit SoC Demo project: https://www.intel.com/content/www/us/en/docs/programmable/848957/2025-1/soc-design-example-prerequisites.html Then, i have compiled yolo_v3_tiny_tf model with no folding and device fpga, cpu to obtain .bin file. When i run the ./run_inference_stream.sh, it get this error: root@arria10:~/app# ./run_inference_stream.sh Runtime version check is enabled. [ INFO ] Architecture used to compile the imported model: A10_Performance Using licensed IP Read hash from bitstream ROM... Read build version string from bitstream ROM... Read arch name string from bitstream ROM... Runtime arch check is enabled. Check started... Runtime arch check passed. Runtime build version check is enabled. Check started... Runtime build version check passed. Exception from src/inference/src/cpp/core.cpp:184: Exception from src/inference/src/dev/plugin.cpp:73: Exception from src/inference/src/dev/plugin.cpp:73: Exception from src/plugins/intel_cpu/src/utils/serialize.cpp:145: [CPU] Could not deserialize by device xml header. How can i solve this problem? Thank you. Note: root@arria10:~/app# ls build_os.txt libopenvino_auto_batch_plugin.so build_version.txt libopenvino_auto_plugin.so categories.txt libopenvino_c.so dla_benchmark libopenvino_c.so.2024.6.0 hetero_plugin libopenvino_c.so.2460 image_streaming_app libopenvino_ir_frontend.so libcoreDLAHeteroPlugin.so libopenvino_ir_frontend.so.2024.6.0 libcoreDlaRuntimePlugin.so libopenvino_ir_frontend.so.2460 libformat_reader.so libopenvino_jax_frontend.so libhps_platform_mmd.so libopenvino_jax_frontend.so.2024.6.0 libopencv_core.so.4.8.0 libopenvino_jax_frontend.so.2460 libopencv_core.so.408 libopenvino_pytorch_frontend.so libopencv_highgui.so.4.8.0 libopenvino_pytorch_frontend.so.2024.6.0 libopencv_highgui.so.408 libopenvino_pytorch_frontend.so.2460 libopencv_imgcodecs.so.4.8.0 libopenvino_template_extension.so libopencv_imgcodecs.so.408 libopenvino_tensorflow_lite_frontend.so libopencv_imgproc.so.4.8.0 libopenvino_tensorflow_lite_frontend.so.2024.6.0 libopencv_imgproc.so.408 libopenvino_tensorflow_lite_frontend.so.2460 libopencv_videoio.so.4.8.0 plugins.xml libopencv_videoio.so.408 results.txt libopenvino.so run_image_stream.sh libopenvino.so.2024.6.0 run_inference_stream.sh libopenvino.so.2460 streaming_inference_app libopenvino_arm_cpu_plugin.so
JTAG Chain Broken – Unable to Program Agilex 5 Modular Development Board
Hi, I recently started working with the Agilex 5 Modular Development Board, and it suddenly can no longer be programmed. The USB cable in use is known to be working. When I connect the cable, it is detected, but when I run the “Auto Detect” option in the Quartus Programmer, I receive the following message: When running the JTAG Chain Test, I see the following result: I also tried using the Configuration Debugger, but when I attempt to select the hardware cable, I encounter Error code 87: I would appreciate any help in resolving this issue, and I can provide additional details or logs if needed.
DE10-nano HPS boot from EPCS
Hello, I am currently trying to setup LoanIO on a DE10-nano so i can access the PHYs RGMII0 signals from the FPGA. According to the Cyclone V Manual, the HPS registers have to be set up in the preloader for this. So i follow this guide to build the u-boot-spl: https://www.rocketboards.org/foswiki/Documentation/UpdatePreloaderUBootOnDE10NanoOnWindows10OS Then converted it to a .hex file to initialize the on-chip Memory following to this guide: https://www.rocketboards.org/foswiki/Documentation/BootFromFPGA150 Then recompile the design and finally generate the .jic file to configure everything from EPCS64. Now the FPGA part of my design is running but the preloader does not seem to be executed. I am using Quartus Prime 24.1std and u-boot branch socfpga_v2025_07. I also tried setting SPL_TEXT_BASE to 0xC0000000 and CONFIG_SPI_BOOT inside the menuconfig. Am i missing any relevant flags or is the problem elsewhere? Best regards.
"No Video Input" message on the monitor running Display port design example for Arria 10 SX SoC
Hi, I am stuck trying to test Display Port on my Arria 10 SX SoC board. I need TX only design example. I tried to download full design example from Intel/Altera web sites, but mostly they are for older Quartus versions or for FMC daughter cards. I want to test Display Port onboard connector. My Quartus version is Quartus Pro 25.1, device - 10AS066N3F40E2SG1 Also I tried to generate design example in Platform Designer and I succeeded to receive EDID from monitor and it seems that handshake is done, but I see only "No Video Input" message on my monitor. I spend more than a week discovering the issue and I assume that PMA settings might be wrong or incorrect link rate/clock frequencies. Thanks in advance for any help!
SFP+ ref clock (program clock cleaner?)
Hi, I'm working with Arria 10 SoC dev kit and trying to use SFP+ ref clock. I don't have any information on ref clock frequency on LMK_SFPCLK(P/N) that comes from clock cleaner (U26). I need to have ref clock by like 322.265625 Mhz, so do I need to program U26 (clock cleaner)?? Where I can find the software to do so? Another question is what is the default frequency running on LMK_SFPCLK ? Thanks
Question about the schematic link for Agilex-7 F-Series Dev Kit (DK-DEV-AGF014EA)
Hello, I downloaded the schematic from this page: https://www.altera.com/products/devkit/a1jui0000049uu7mam/agilex-7-fpga-f-series-development-kit-p-tile-and-e-tile However, the schematic appears to be for a different evaluation board — it looks like a PCIe Root Complex board, not the Agilex-7 F-Series Dev Kit shown in the photo. Could you please confirm whether this is the correct schematic for the Agilex-7 F-Series Development Kit, or if the link points to the wrong file? Thank you, Kashiwagi
