platform
367 TopicsSOLVED: BSP Editor NullPointerException on Debian 13 Linux
SOLVED: BSP Editor "New BSP" menu command is grayed out, so can't make any new BSP's, and opening any existing one from another computer throws: SEVERE: Available BSP type values for the --type argument are: [] SEVERE: BSP type "hal2" unknown. SEVERE: NullPointerException Based on other forum posts with a similar error, it seems like this is because the BSP Editor couldn't locate some of its own files. That seems likely here too since this is the first time it's used on this computer. But there's no problematic install path etc since I used the default. THERE ARE NO SPACES IN THE INSTALL PATH NOR THE PROJECT PATH. Everything else is working already for the Max 10: I can generate with Platform Designer, synthesize with Quartus, program SRAM with SignalTap, debug Nios V with RiscFree. Details are: Quartus Prime Lite 25.1std.0 Build 1129 10/21/2025 SC Lite Patches: None OS: Debian 13. This is what Ubuntu is based on, so it's very similar. And like I said everything else already works. USB came online already, not too hard. All it took was the Altera udev rules file 92 as usual, and the correct LD_LIBRARY_PATH so jtagd could find its own shared libs. Installed quartus into regular user account, not whole system, not as root. This is offered as an option in the installer if I recall correctly. Install path is the installer's default: /home/myuser/altera_lite/25.1std The project files are irrelevant here, since BSP Editor is already off-track as soon as it launches. "New BSP" is grayed out. SOLVED: BSP Editor is unable to find its own files without Altera's environment vars, which are provided when running inside niosv-shell. That's nonsensical to me, since any brain-dead program off the street can detect where its own binary loaded from, on any OS, and walk up the path from there to find the rest of its files, as a default if no env vars were provided. That's the first line of every binary or Tcl script I've ever written. Quartus main GUI seems to do it exactly that way. Anyone else struggling with this inexplicable rough edge should make sure your desktop's launcher icon invokes niosv-shell first, like this: altera_lite/25.1std/niosv/bin/niosv-shell --run altera_lite/25.1std/niosv/bin/niosv-bsp-editor To Altera: if you're struggling to maintain or improve your software because it relies on Tcl, contact me through my forum account. I could clean up a whole mess of rough edges like this one, and some other much-needed improvements.8Views0likes0CommentsStarting Quartus GUI fails in docker version
Hi, Recently I found out Quartus is available for docker. I started to test and compile process worked well on an existing design with 25.1 Standard Edition on both native SUSE Linux and WSL (SUSE as well). But when I wanted to start the GUI, I got back the following error (in both cases): /mnt/c/Windows/system32> docker run --net=host alterafpga/quartus-std:25.1std-all quartus *** Fatal Error: Segment Violation at (nil) Module: quartus Stack Trace: 0x289a2: abort + 0x182 (c.so.6) 0xae55a: QtPrivate::lcNativeInterface() [clone .cold] (Qt6Core.so.6) 0xaedc4: QMessageLogger::warning(char const*, ...) const (Qt6Core.so.6) 0xf9dc2: QGuiApplication::restoreOverrideCursor() [clone .cold] (Qt6Gui.so.6) 0x18e5a1: QGuiApplicationPrivate::createPlatformIntegration() + 0x641 (Qt6Gui.so.6) 0x18ef00: QGuiApplicationPrivate::createEventDispatcher() + 0x30 (Qt6Gui.so.6) 0x1461f5: QCoreApplicationPrivate::init() + 0xbe5 (Qt6Core.so.6) 0x1921b3: QGuiApplicationPrivate::init() + 0x33 (Qt6Gui.so.6) 0x18bc59: QApplicationPrivate::init() + 0x9 (Qt6Widgets.so.6) 0xb3899: AFCQ_APP::AFCQ_APP(int&, char**) + 0x13 (gcl_afcq) 0x6863a: QUI_APP::QUI_APP(int&, char**) + 0x1e (sys_qui) 0x14fb9: QGQ_APP::QGQ_APP(int&, char**) + 0x9 (sys_qgq) 0x38b8: qgq_main(int, char const**) + 0x48 (quartus) 0x3e540: msg_main_thread(void*) + 0x10 (ccl_msg) 0x5c1c: thr_final_wrapper + 0xc (ccl_thr) 0x3e60a: msg_thread_wrapper(void* (*)(void*), void*) + 0x6e (ccl_msg) 0xc046: mem_thread_wrapper(void* (*)(void*), void*) + 0x96 (ccl_mem) 0x9188: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err) 0x5c5f: thr_thread_wrapper + 0x15 (ccl_thr) 0x4050a: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa8 (ccl_msg) 0x39d5: main + 0x26 (quartus) 0x2a28b: __libc_start_main + 0x8b (c.so.6) 0x37aa: _start + 0x2a (quartus) End-trace Is this a compatibility issue with my Linux version? Or do I make something wrong? Best regards, Istvan28Views0likes2CommentsQuesta-ModelSim UI scaling problems in Linux
Hello Has anybody been able to solve the issue of UI of Questa not scaling correctly on linux with wayland? I am using Ubuntu 26.04 with wayland and UI is just tiny, icons, are so small i cannot read any text. When opening a new project, file explorer is also tiny. Fonts i could change in the config file but icons, menus and everything else is just extremely small. Problem is even worse on high resolution displays. Regards, Haris80Views0likes3CommentsIssue with MIPI CSI2 Encrypted IP File During Project Integration
Hi, I am working on a project where I have integrated two separate projects into a single top-level design. Project A includes the MIPI CSI2 IP and other related components. Project B contains the logic to process the output data generated by the MIPI CSI2 IP. When I compile both projects individually, they complete successfully without any errors. However, after instantiating both projects together in a single top-level wrapper, I encounter a compilation error originating from the generated encrypted file of the MIPI CSI2 IP. I have attached the error snapshot for your reference. Could you please help identify the possible cause of this issue? Is there any known limitation or configuration requirement when integrating the MIPI CSI2 IP with additional logic in the same top-level design? Thanks.75Views0likes4CommentsNIOS-V Shell: qsys-generate not found
Hello, we are using makefiles to build our Quartus & QSYS projects. Since we switched from NIOS-II shell to NIOS-V shell, I realized that qsys-generate is no longer accesible. The command "qsys-generate.exe" is either misspelled or was not found. Other quartus commandline tools remain available in NIOS-V Shell: quartus_sh/quartus_sh.exe quartus_fit/quartus_fit.exe The command qsys-generate.exe does exist, it is simple not added to the path in NIOS-V shell. What is the correct way to invoke qsys-generate.exe from within NIOS-V shell? best regards FabianSolved84Views0likes5CommentsHow to create a Packaged Subsystem in TCL
I am hoping to create a script which will automatically package the IP I am working on as a packaged subsystem. So far, I have automated the creation of an IP directory which describes a new component using a _hw.tcl file and the various source files. I believe the next step is to take this component, instantiate it in a Platform Designer system, and create a Packaged Subsystem using it. I am also hoping that I can parameterise and hide/modify ports of the packaged subsystem, like I can with the _hw.tcl component description. I am encountering a problem; I am running the following command: qsys-script --script=create_packaged_subsystem.tcl --new-quartus-project=my_project_name However, the script fails for the following reason: Error: invalid command name "set_package_property" Here is the script itself (more or less a copy-and-paste from the GUI): package require -exact qsys 26.1 set_package_property NAME "packagename" set_package_property DISPLAY_NAME "PackageName" set_package_property VERSION "1.0" set_package_property GROUP "GroupName" set_package_property DESCRIPTION "A descripton." set_package_property ELABORATION_CALLBACK elaboration_callback set_package_property EXTRACTION_CALLBACK extraction_callback add_fileset synth_fileset QUARTUS_SYNTH fileset_callback "Quartus Synthesis Fileset" add_fileset sim_verilog_fileset SIM_VERILOG fileset_callback "Simulation Verilog Fileset" proc elaboration_callback {} { enable_all_instances } proc extraction_callback {} { extract_modules } proc fileset_callback { output_name } { generate_all_instances } Any help would be hugely appreciated, on this issue and on my general workflow. Also if it is possible to encrypt packaged subsystems or components using Quartus I'd be keen to know. Thanks!106Views0likes5CommentsMailbox Client IP - SEND_CERTIFICATE command through FPGA fabric
Hi colleagues, under Agilex3C (A3CY135BM16A) Non-HPS with Quartus 26.1 (latest SDM, latest IPs) how one can send compact certificates to SDM through the internal FPGA fabric? I tried it with Mailbox Client (1024/1024 FIFO depth, AXI accelerator path disabled) + SPI slave/JTAG Avalon Master, all other SDM commands (incl. the complicated ones like SPI programming with larger payloads) are working fine except this one. The error I get back all the time is 0xF00000FF (which appears as 0x3FF in SDM level1 log), so generic error, no explanation. When I load the same certificate over JTAG (external JTAG not via JTAG Avalon bridge to Mailbox Client), then it is working fine (so signature and certificate content is right). I tried both burning fuse or just loading virtual fuse with/without test bit. All gives back this same answer if it has been sent over FPGA Fabric SDM mailbox. Does anyone know any example project for this? (I tried to make it work based on ATF-A mailbox driver's VAB certificate loading command implementation (which theoretically should accept other certificates too). I believe this is something supposed to work without HPS. (otherwise you should leave JTAG enabled in your system). Links: arm-trusted-firmware/plat/altera/soc/common/include/socfpga_mailbox.h at socfpga_v2.14.0 · altera-fpga/arm-trusted-firmware arm-trusted-firmware/plat/altera/soc/common/soc/socfpga_mailbox.c at socfpga_v2.14.0 · altera-fpga/arm-trusted-firmware Thanks, Peter457Views0likes8CommentsHow to specify the library for files in the Component Editor?
I am making a custom IP component in Quartus Prime 26.1. Most files are simply part of the "work" library, however there is at least one file which needs to be compiled under a specific library name. I have created my own _hw.tcl file, which is working fine. The problem is, that when I include all my files, I do not know how to specify the library each file should be compiled into. This results in an error message when synthesising: VHDL Use Clause at MyFile.vhd(29): design library "mylib" does not contain primary unit "mylibcomponents". It would seem natural that there'd be an attribute or something you can apply to a file or fileset, which would specify the library; however, I've been unable to find anything. Many thanks in advance for any guidance!Solved114Views0likes5CommentsA5EG013BB18A OPN is visible in Quartus but not listed in Program File Generator
Hi everyone, I am currently working on programming an SCM FPGA board using Intel Quartus 25.1 . Our target FPGA OPN is A5EG013BB18A. I need to generate a .jic file from a .sof file by using the Program File Generator. However, when I try to select the FPGA Device in the Program File Generator, we cannot find A5EG013BB18A in the device list. The strange thing is that A5EG013BB18A can be seen in other places within Quartus, but it is not shown only in the Program File Generator device selection list. I have attached screenshots and related files showing: 1. The device can be seen in Quartus 2. The Program File Generator FPGA Device selection list 3. The content of .ini file and the .qsf file Could anyone help confirm the following? Is A5EG013BB18A supported in the Program File Generator? 2. Is there any specific .ini file setting or placement required for the Program File Generator to show this OPN? 3. Is a specific Quartus version or device package required? 4. Is there any known limitation where an OPN is visible in Quartus but not available in the Program File Generator? Any advice or reference would be appreciated. Thank you.258Views0likes12Comments