Linux not booting - can't get kernel image
Hi, I'm having trouble booting to Linux after migrating a project to the newest GSRD 2.0 (Quartus 25.3). I'm using an Agilex 5 FPGA E-Series 065B Premium Devkit. The project was based in the GSRD for Quartus 25.1 (QPDS25.1_REL_GSRD_PR) and had a few modifications, working in version 25.1 with the default device-tree. I'm guessing this might be something related to differences in the device-tree between GRSD 2.0 and the previous version ? I've tried looking around but there's so many .dts and .dtsi files that I'm a bit lost. Any advice appreciated.
Agilex 5 with HPS Cryptographic services and bootflow
Hi I have a question regarding boot flow on agilex 5 with HPS with security in mind. I am aware how this is typically implemented on other SoCs like NXP but as for the Agilex - I just started working on this SoC From what I understand (based on the docs and tf-a source code in particular VAB part) the flow is the following: SDM verfies fsbl signature and loads it SDM releses HPS from reset Fsbl loads next stages (BL31 BL33) each time communicating with SDM through mailbox asking SDM to verify the image signaturure Then we can be sure that we only use legitimate binaries. Am I right? I have found in the agilex 5 product table that some variants are equipped with Cryptographic services and some not. Are these Cryptographic services needed to perform the above flow? If the variant I have is not equipped with such IP is there any other way to securely boot all boot chain up to Linux?
Arria 10 SoC Dev Kit Baremetal HPS examples issue & workflow
Hi, I recently acquired an Arria 10 SoC dev kit but I'm really struggling to run either the examples on embedded-software/bare-metal or the ones included in SoC EDS pro 20.1, trying to follow the instructions for both of them, they seem to rely on a old version of SoC EDS which included within ARM DS-5 and the toolchain, but now SoC EDS & ARM DS are separated and I cannot build the examples. With the new applications the flow for using this examples should remain the same? I mean: use Pogrammer to program the included .sof inside ghrd (or generate a updated one) -> open ARM-DS from SoC-EDS with environmental variables assigned and build with new toolchain arm-none-eabi -> run from ARM-DS (can i without license?) Seems like most of the tools used for running this examples have been discontinued (for example ) so at this point I don't know which workflow should I actually follow. PD: finally I was able to generate de application.axf from this example Altera-SoCFPGA-HardwareLib-16550-CV-GNU with an old toolchain but I don't know how to program it without a license, for now I don't want to debug anything, just do some simple tests printing by uartAgilex 5 HPS TEE
Hi, Is Arm Trust Zone supported on HPS? If so is the implementation of TEE supported on Agilex 5? I've checked TF-A sources and it seems that BL2 on this platform loads only BL31 and BL33. How about BL32? Is there an OP-TEE support? If not, are there any plans to provide it in the nearest feature?Agilex 5 with HPS
Hi, I have a question regarding Agilex 5 with HPS. I intend to deliver to the client a device based on Agilex 5 and HPS, but initially the HPS must remain fully offline. In other words, once the device is shipped, I need to ensure with 100% certainty that no software or program can be executed on the HPS, and that there is no possible way for the client to interact with or enable it prematurely. At the same time, I need to retain the ability to remotely deploy a new FPGA bitstream at a later stage, which will enable the HPS once the HPS software development is completed. Is such a workflow achievable on this platform?
Cyclone V: how to boot Linux from QSPI?
I am building a system with Buildroot and Barebox as the bootloader. I can generate a working SD card image. Now, I want to transpose this to a 64MiB NOR QSPI flash on the SoM. I read the HPS boot guide, that describes the required SD card partition layout, but it is not very verbose about the QSPI... I read that UBI + UBIFS is very common for NOR flash. I understand that it is well suited for the rootfs. But where should I place the pre-loader? Could someone give more details to install Linux on a QSPI and boot from it?
HPS SDRAM Calibration Failed
To whom it may concern, The HPS of a Cyclone V SoC based board that I designed is failing the booting process. In which the following error message is outputted to the console: U-Boot SPL date and time SDRAM Calibration Failed. ERROR ### Please Reset the board ### I’m trying to determine the cause of the SDRAM calibration failure by enabling calibration reporting as indicated in: https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/enabling-the-debug-report-for-arria.html https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/determining-the-failing-calibration.html but I’m only getting the above mentioned message without an indication of the failing SDRAM stage and cause. please advise on how to get the preloader to output debug insights to the console. Please note that the approach described in the link below was used to create the Preloader: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 Also, please advise on the sequence of failure messages that are outputted by the Preloader. Regards,SDRAM calibration failed.
Hello, after Enpirion stopped selling some of the parts we used on our board, we had to redesign it. We assembled ten boards, and on two of them, I’m now getting an SDRAM calibration error in U-Boot. I’d like to enable the SDRAM calibration report to understand the cause of the error. However, the described method of adding. #define RUNTIME_CAL_REPORT 1 in the sequencer_defines.h file didn’t work. I generated the files using the QTS filter script, but there was no change. Could you please tell me how to properly enable the SDRAM calibration report so I can debug the issue?
