What is an MD5 checksum value and what is it used for?
Description An MD5 checksum is a 32-character hexadecimal number that is computed on a file. If two files have the same MD5 checksum value, then there is a high probability that the two files are the same. After downloading an Altera software installation package, you can compute the MD5 checksum on the installation file. Use the computed MD5 checksum to compare against the MD5 checksum provided for that installation file on the download page. By doing this, you can verify the integrity of your download. There are a variety of MD5 checksum programs available on the Internet. Related Articles How do I determine if I have the right executables for running Modelsim Altera Starter Edition in the Quartus II software version 14.1?Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
Description You may get this warning when simulating some DSP Builder® designs under Modelsim®. These warning messages do not have any effect on your simulation results, and can be ignored. Resolution These warnings (and all others like them) can be suppressed by either of two methods: Suppress via Modelsim GUI: Open the Simulation dialog box (Options menu). Set the option Suppress Warnings from Synopsys Packages to On. Click OK. Search for the *_atb.do file in your project directories, look for the comment "Disable some warnings ...", and comment out a later line as follows: # Disable some warnings that occur at the very start of simulation quietly set StdArithNoWarnings 1 run 0ns # quietly set StdArithNoWarnings 0 run -all Related Articles ASSERT/WARNING from package ieee.STD_LOGIC_ARITH, Built-in function result set to 'X' due to a ('U', 'X', 'W', 'Z', '-') in an operand / Built-in function CONV_INTEGER/TO_INTEGER argument too large Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0! (ModelSim, VHDL Output File (.vho))Why do I get a VHDL Use Clause error in Quartus II when compiling a VHDL file generated by DSP Builder?
Description You will get a VHDL Use Clause error in Quartus II when compiling a VHDL file generated by DSP Builder if you have not added the appropriate DSP Builder library files to your Quartus II project. These library files should already be added to the project for you if you run Quartus II from within SignalCompiler or if you use the Quartus II tcl script generated by DSP Builder. However, if you are running the Quartus II compile outside of SignalCompiler and are not using the Quartus II tcl script, you will need to set these library files up manually. The text of the error will look similar to: Error: VHDL Use Clause error at <filename>.vhd: design library does not contain primary unit dspbuilder block Error: Ignored construct <entity name> at <filename>.vhd because of previous errors To compile DSP Builder generated VHDL files in Quartus II, you must have the path to the DSPBUILDERPACK.vhd and DSPBUILDER.vhd files specified in your Quartus II project. These files are located in the <DSP Builder install directory>\altlib directory. To add these files, select Add/Remove Files in Project... under the Project menu in Quartus II. Browse to the <DSP Builder install directory>\altlib directory and select the DSPBUILDERPACK.vhd and DSPBUILDER.vhd files and click OK to add the files. The compilation order of the files is important. DSPBUILDERPACK.vhd must be compiled before DSPBUILDER.vhd. Once you have included the files, rerun your Quartus II compile.Error: (vlog-13067) ./../../src/altera_ldpc_pkg.sv(1.0): Syntax error, unexpected non-printable character with the hex value '0x8b'.
Description Due to a problem with the LDPC FPGA IP in Quartus® Prime Pro Edition Software version 17.1 targetting Stratix® 10, you may observe the above error when compiling the simulation design example generated by the IP configured with WiMedia 1.5 standard and encoder mode in Modelsim. Resolution To work around this problem, comment out the following lines in the msim_setup.tcl: 1. eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../src/altera_ldpc_pkg.sv" -work work 2. eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../src/altera_ldpc_wimedia_enc.sv" -work workCan anti-virus software prevent me from successfully downloading and installing the Altera software version 10.0?
Description Altera recommends that you disable any anti-virus scanner while downloading and installing the Altera® software using the Altera Software Installer version 10.0. Some anti-virus scanners prevent the Altera Software Installer from properly downloading and installing the Altera software to your computer. In some cases, the installer program may indicate that the download and installation completed successfully, when in fact it did not. Particular anti-virus scanners that may prevent a successful download and installation of the Altera software include AVG anti-virus software, ESET NOD32 anti-virus software, VirusBuster anti-virus software, and McAfee anti-virus software. However, Altera recommends that you disable any anti-virus scanner while downloading and installing using the Altera Software Installer version 10.0. This problem is fixed in the Altera Software Installer version 10.0Rev2. You can download this version of the Altera Software Installer from the Download Center. Related Articles Why does my Quartus II software download fail with the Internet Explorer 6 or the Internet Explorer 7 browser? What are the options to download and install the Altera Complete Design Suite (ACDS) version 10.0? How do I download and install the Altera software version 10.0 for Windows from the command line?What versions of Matlab are supported by DSP Builder version 11.0?
Description Version 11.0 of DSP Builder and the DSP Builder Advanced Blockset supports the following Matlab/Simulink versions: 2009a, 2009b, 2010a, 2010b and 2011a Please note that the information provided in the DSP Builder Handbook v11.0 Chapter 3 Installing DSP Builder, Table 3-1 is incorrect. 32-bit and 64-bit Matlab version support is as follows: DSP Builder Standard Blockset 64bit-Matlab on Linux only. 64bit Matlab support for Windows is currently scheduled for a future release of DSP Builder. DSP Builder Advanced Blockset 64bit Matlab supported on Windows and Linux.Why do I see invalid read data when the DSP Builder memory interface bus has an NCO or FIR attached?
Description You may see invalid read data at the end of a memory read burst or at the end of any single memory read if you have an NCO or FIR component on your DSP Builder memory interface bus. Resolution This is due to a problem with the Quartus® II software. The workaround is to move the NCO or FIR filter to a non-zero address. This is scheduled to be fixed in a future release of the Quartus® II software.Does the Clocked Video Output (CVO) IP core support SDI 720p24 format?
Description The Altera® Clocked Video Output (CVO) IP core does not support the SDI 720p24 format. This is because the 4125 total horizontal lines of the SDI 720p24 format exceeds the 4096 maximum horizontal lines supported by the CVO. Resolution There is no plan to update the CVO IP core to support the SDI 720p24 format. However, this format will be supported in the Clocked Video Output II (CVO II) IP core in a future release of the Quartus® software.Why is my Native Fixed Point DSP block showing an unexpected latency in simulation?
Description For some combinations of parameters, simulators and RTL coding styles, the latency of this block in simulation deviates from the expected latency by , - one clock. Actual hardware exhibits the expected latency. This behavior will be seen, for example, if the clock driving the DSP block is a delayed version of the clock generating the input data, thus introducing more simulation delay for the input clock than for the input data. Resolution To work around this problem, you must ensure that delays between the clock that generates input data to the DSP block, and the input clock of the DSP block, are balanced by delays on the input data. Alternatively ensure that the input data arrives at a later absolute time, or a later simulation delta delay time, compared to the input clock of the DSP block. Note that such things as more assignment statements on the clock path vs. the data path will cause simulation delta delay differences between those paths. To accomplish this, modify your testbench to: Ensure the clock generating inputs to the Native DSP block is exactly the same signal as the clock input to the Native DSP block. If #1 is not feasible, delay the input data relative to the clock. For example, consider the following original RTL code: Original RTL: clk_gen: process begin clk_orig <= \'0\'; wait for 5 ns; clk_orig <= \'1\'; wait for 5 ns; end process; ... if (rising_edge(clk_orig)) then ax <= ax 1; ay <= ay - 1; end if mac_test_bad_style: mult_acc port map ( ... ax => std_logic_vector(ax), -- [in] ay => std_logic_vector(ay), -- [in] clk => ("00" & clk_orig), -- [in] resulta => resulta2, -- [out] ... ); resulta2 will show one clock less latency than expected. Note that the concatenation of "00 & clk" in the multiplier\'s clk port assignment adds a simulation delta delay from the "clk_orig" which generates the input data. Possible workarounds include: Example 1, Recommendation: Use a 3-bit clock throughout You can generate the multiplier\'s 3-bit clock directly and use the active bit to clock the input data: clk_gen: process begin clk3bit <= \'000\'; wait for 5 ns; clk3bit <= \'001\'; wait for 5 ns; end process; ... if (rising_edge(clk3bit(0))) then ax <= ax 1; ay <= ay - 1; end if mac_test_bad_style: mult_acc port map ( ... ax => std_logic_vector(ax), -- [in] ay => std_logic_vector(ay), -- [in] clk => (clk_3bit), -- [in] resulta => resulta2, -- [out] ... ); Example 2, Alternate Recommendation: add corresponding delay to the input data The \'clk => ("00" & clk_orig)\' statement causes the \'clk" port to have an additional simulation delta delay from \'clk_orig\' that\'s driving the data. To overcome this, you can use the original clk_gen process and just add simulation delta delays to the data with assignment statements. clk_gen: process (same as original) ax_del <= ax; ay_del<=ay; mac_test_bad_style: mult_acc port map ( ... ax => std_logic_vector(ax_del), -- [in] ay => std_logic_vector(ay_del), -- [in] clk => ("00" & clk_orig), -- [in] resulta => resulta2, -- [out] ... );