What is an MD5 checksum value and what is it used for?
Description An MD5 checksum is a 32-character hexadecimal number that is computed on a file. If two files have the same MD5 checksum value, then there is a high probability that the two files are the same. After downloading an Altera software installation package, you can compute the MD5 checksum on the installation file. Use the computed MD5 checksum to compare against the MD5 checksum provided for that installation file on the download page. By doing this, you can verify the integrity of your download. There are a variety of MD5 checksum programs available on the Internet. Related Articles How do I determine if I have the right executables for running Modelsim Altera Starter Edition in the Quartus II software version 14.1?Error: <module name>The source has a data signal of <number> bits, but the sink does not.
Description Due to a problem in Quartus® II/DSP Builder 14.1, you will see the above error on components which have more than one Avalon® ST interface (AVST). You may also notice in the Qsys heirarchy view that one of the AVST interfaces has no signals, and that there is an extra interface named "exp" which also has no signals. Resolution To work around the problem, find and edit the Qsys generated <module name>_hw.tcl file for the component in the error message. Make the signal names unique between all avalon_streaming sinks, and between all avalon_streaming sources. For example you can add a "1" to all the names on one component. Also comment out the "exp" interface. For example: Qsys generated version: ... # Interface AStInput add_interface AStInput avalon_streaming sink set_interface_property AStInput errorDescriptor "" set_interface_property AStInput maxChannel 255 set_interface_property AStInput readyLatency 0 set_interface_property AStInput ASSOCIATED_CLOCK clock set_interface_property AStInput ENABLED true set_interface_property AStInput dataBitsPerSymbol 17 add_interface_port AStInput input_ready ready Input 1 set_port_property input_ready VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput sink_valid valid Input 1 set_port_property sink_valid VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput sink_channel channel Input 8 add_interface_port AStInput sink_data data Input 17 add_interface_port AStInput sink_sop startofpacket Input 1 set_port_property sink_sop VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput sink_eop endofpacket Input 1 set_port_property sink_eop VHDL_TYPE STD_LOGIC_VECTOR # Interface AStInput1 add_interface AStInput1 avalon_streaming sink set_interface_property AStInput1 errorDescriptor "" set_interface_property AStInput1 maxChannel 255 set_interface_property AStInput1 readyLatency 0 set_interface_property AStInput1 ASSOCIATED_CLOCK clock set_interface_property AStInput1 ENABLED true set_interface_property AStInput1 dataBitsPerSymbol 17 add_interface_port AStInput1 input_ready ready Input 1 set_port_property input_ready VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput1 sink_valid valid Input 1 set_port_property sink_valid VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput1 sink_channel channel Input 8 add_interface_port AStInput1 sink_data data Input 17 add_interface_port AStInput1 sink_sop startofpacket Input 1 set_port_property sink_sop VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput1 sink_eop endofpacket Input 1 set_port_property sink_eop VHDL_TYPE STD_LOGIC_VECTOR ... # Interface exp add_interface exp conduit end set_interface_property exp ENABLED true Modified version: # Interface AStInput add_interface AStInput avalon_streaming sink set_interface_property AStInput errorDescriptor "" set_interface_property AStInput maxChannel 255 set_interface_property AStInput readyLatency 0 set_interface_property AStInput ASSOCIATED_CLOCK clock set_interface_property AStInput ENABLED true set_interface_property AStInput dataBitsPerSymbol 17 add_interface_port AStInput input_ready ready Input 1 set_port_property input_ready VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput sink_valid valid Input 1 set_port_property sink_valid VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput sink_channel channel Input 8 add_interface_port AStInput sink_data data Input 17 add_interface_port AStInput sink_sop startofpacket Input 1 set_port_property sink_sop VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput sink_eop endofpacket Input 1 set_port_property sink_eop VHDL_TYPE STD_LOGIC_VECTOR # Interface AStInput1 add_interface AStInput1 avalon_streaming sink set_interface_property AStInput1 errorDescriptor "" set_interface_property AStInput1 maxChannel 255 set_interface_property AStInput1 readyLatency 0 set_interface_property AStInput1 ASSOCIATED_CLOCK clock set_interface_property AStInput1 ENABLED true set_interface_property AStInput1 dataBitsPerSymbol 17 add_interface_port AStInput1 input1_ready ready Input 1 set_port_property input1_ready VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput1 sink1_valid valid Input 1 set_port_property sink1_valid VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput1 sink1_channel channel Input 8 add_interface_port AStInput1 sink1_data data Input 17 add_interface_port AStInput1 sink1_sop startofpacket Input 1 set_port_property sink1_sop VHDL_TYPE STD_LOGIC_VECTOR add_interface_port AStInput1 sink1_eop endofpacket Input 1 set_port_property sink1_eop VHDL_TYPE STD_LOGIC_VECTOR ... # Interface exp # add_interface exp conduit end # set_interface_property exp ENABLED true This is scheduled to be fixed in a future release of the Quartus II/DSP Builder software.Error in 'mdm/HDLImport' while executing C MEX S-function 'sGeneric', (mdlStart), at time 0.0.
Description You may receive the error message below when running a Simulink® simulation which includes the NCO Megacore® block using DSP Builder in an Arria® V design: Error in 'mdm/HDLImport' while executing C MEX S-function 'sGeneric', (mdlStart), at time 0.0. Caused by: Unexpected (char*) exception from MEX file. String is:MLIB_UINTEGER::bit() called with illegal bit_position .. Resolution To workaround this issue in Quartus® II software version 13.0 SP1, please follow the steps below: 1. Close DSP Builder (if there is one running) 2. Copy the content of the appropriate attached compressed files to your DSP Builder bin64 directory (i.e. <13_0_sp1_install_dir>/quartus/dsp_builder/bin64) 3. Re-start DSP Builder For Windows 64: 13_0sp1_windows64.zip - alt_dspbuilder_mAltr_PvoIp.mexw64 - alt_dspbuilder_mAltr_Pvo.mexw64 - alt_dspbuilder_ParseVo.mexw64 - SimgenExport.dll For Linux 64: 13.0sp1_linux64.tar.gz - alt_dspbuilder_mAltr_PvoIp.mexa64 - alt_dspbuilder_mAltr_Pvo.mexa64 - alt_dspbuilder_ParseVo.mexa64 - libSimgenExport.so This issue has been fixed in Quartus II software version 13.1 and later.Error(15360): DSP block WYSIWYG primitive "u0|a10_native_fixed_point_dsp_0|twentynm_mac_component" has unconnected port ACLR[0] -- port must be connected because corresponding register is used
Description Due to a problem in the Quartus® Prime Pro Edition Software version 20.3 and later, you may see this error when you are using the Arria® 10 Native Fixed Point DSP IP. The error happens because the user is enabling registers for "az" and "bz" but not using the "az" and "bz" ports. Resolution To avoid this error, disable the registers for "az" and "bz" in Data "z" Configuration if you are not using "az" and "bz" ports. This error is planned to be fixed in a future release of the Quartus® Prime Pro Edition Software.Warning (10631): VHDL Process Statement warning at <filename>.vhd(): inferring latch(es) for signal or variable "<name>", which holds its previous value in one or more paths through the process
Description Due to a problem in the Quartus® II software, you may see this warning if your code implements an incrementer or decrementer with an asynchronous reset where some of the bits remain constant. For example, with the following code, the Quartus II software will erroneously report a warning for the lower bits: process (reset, clk) begin if reset = '1' then minus_8_count_int <= TO_UNSIGNED(16,5); elsif (rising_edge(clk)) then minus_8_count_int <= minus_8_count_int - 8; end if; end process; As the counter decrements by 8, the lower 3 bits are unused and before they get optimized away, the Quartus II Integrated Synthesis warns that they are latches. Resolution It is safe to ignore the warning in this case as no latches are implemented.Why isn't the chainout adder used by my inferred DSP?
Description Due to a problem in the Quartus® II software version 13.1 and earlier, you may see an adder implemented in registers rather than being absorbed into a DSP block. This occurs when the tool detects a loop going through the DSP block and adder. Resolution To work around this problem, set a keep attribute on the signal looping from the DSP output to it\'s input. This prevents the loop from being detected. Verilog HDL example wire feedback_wire /*synthesis keep*/ VHDL example signal feedback_wire : std_logic; attribute keep: boolean; attribute keep of feedback_wire: signal is true;Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
Description You may get this warning when simulating some DSP Builder® designs under Modelsim®. These warning messages do not have any effect on your simulation results, and can be ignored. Resolution These warnings (and all others like them) can be suppressed by either of two methods: Suppress via Modelsim GUI: Open the Simulation dialog box (Options menu). Set the option Suppress Warnings from Synopsys Packages to On. Click OK. Search for the *_atb.do file in your project directories, look for the comment "Disable some warnings ...", and comment out a later line as follows: # Disable some warnings that occur at the very start of simulation quietly set StdArithNoWarnings 1 run 0ns # quietly set StdArithNoWarnings 0 run -all Related Articles ASSERT/WARNING from package ieee.STD_LOGIC_ARITH, Built-in function result set to 'X' due to a ('U', 'X', 'W', 'Z', '-') in an operand / Built-in function CONV_INTEGER/TO_INTEGER argument too large Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0! (ModelSim, VHDL Output File (.vho))What versions of Matlab are supported by DSP Builder version 11.0?
Description Version 11.0 of DSP Builder and the DSP Builder Advanced Blockset supports the following Matlab/Simulink versions: 2009a, 2009b, 2010a, 2010b and 2011a Please note that the information provided in the DSP Builder Handbook v11.0 Chapter 3 Installing DSP Builder, Table 3-1 is incorrect. 32-bit and 64-bit Matlab version support is as follows: DSP Builder Standard Blockset 64bit-Matlab on Linux only. 64bit Matlab support for Windows is currently scheduled for a future release of DSP Builder. DSP Builder Advanced Blockset 64bit Matlab supported on Windows and Linux.Does the Clocked Video Output (CVO) IP core support SDI 720p24 format?
Description The Altera® Clocked Video Output (CVO) IP core does not support the SDI 720p24 format. This is because the 4125 total horizontal lines of the SDI 720p24 format exceeds the 4096 maximum horizontal lines supported by the CVO. Resolution There is no plan to update the CVO IP core to support the SDI 720p24 format. However, this format will be supported in the Clocked Video Output II (CVO II) IP core in a future release of the Quartus® software.