What is an MD5 checksum value and what is it used for?
Description An MD5 checksum is a 32-character hexadecimal number that is computed on a file. If two files have the same MD5 checksum value, then there is a high probability that the two files are the same. After downloading an Altera software installation package, you can compute the MD5 checksum on the installation file. Use the computed MD5 checksum to compare against the MD5 checksum provided for that installation file on the download page. By doing this, you can verify the integrity of your download. There are a variety of MD5 checksum programs available on the Internet. Related Articles How do I determine if I have the right executables for running Modelsim Altera Starter Edition in the Quartus II software version 14.1?Why do the links to the help pages for the DSP Builder Advanced example designs not work?
Description Due to a problem in the DSP Builder Advanced example designs the links to the help pages are incorrect. Resolution To work around this problem, perform the following steps Open the file quartus\dspba\Examples\demos.xml in the editor Click Find Enter <file> in the Find field Enter <file>../Docs/Help/ in the replace field Click Replace All Save and close the file This problem is scheduled to fixed in a future release of DSP Builder.Can anti-virus software prevent me from successfully downloading and installing the Altera software version 10.0?
Description Altera recommends that you disable any anti-virus scanner while downloading and installing the Altera® software using the Altera Software Installer version 10.0. Some anti-virus scanners prevent the Altera Software Installer from properly downloading and installing the Altera software to your computer. In some cases, the installer program may indicate that the download and installation completed successfully, when in fact it did not. Particular anti-virus scanners that may prevent a successful download and installation of the Altera software include AVG anti-virus software, ESET NOD32 anti-virus software, VirusBuster anti-virus software, and McAfee anti-virus software. However, Altera recommends that you disable any anti-virus scanner while downloading and installing using the Altera Software Installer version 10.0. This problem is fixed in the Altera Software Installer version 10.0Rev2. You can download this version of the Altera Software Installer from the Download Center. Related Articles Why does my Quartus II software download fail with the Internet Explorer 6 or the Internet Explorer 7 browser? What are the options to download and install the Altera Complete Design Suite (ACDS) version 10.0? How do I download and install the Altera software version 10.0 for Windows from the command line?Error: (vlog-13067) ./../../src/altera_ldpc_pkg.sv(1.0): Syntax error, unexpected non-printable character with the hex value '0x8b'.
Description Due to a problem with the LDPC FPGA IP in Quartus® Prime Pro Edition Software version 17.1 targetting Stratix® 10, you may observe the above error when compiling the simulation design example generated by the IP configured with WiMedia 1.5 standard and encoder mode in Modelsim. Resolution To work around this problem, comment out the following lines in the msim_setup.tcl: 1. eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../src/altera_ldpc_pkg.sv" -work work 2. eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../src/altera_ldpc_wimedia_enc.sv" -work workWarning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
Description You may get this warning when simulating some DSP Builder® designs under Modelsim®. These warning messages do not have any effect on your simulation results, and can be ignored. Resolution These warnings (and all others like them) can be suppressed by either of two methods: Suppress via Modelsim GUI: Open the Simulation dialog box (Options menu). Set the option Suppress Warnings from Synopsys Packages to On. Click OK. Search for the *_atb.do file in your project directories, look for the comment "Disable some warnings ...", and comment out a later line as follows: # Disable some warnings that occur at the very start of simulation quietly set StdArithNoWarnings 1 run 0ns # quietly set StdArithNoWarnings 0 run -all Related Articles ASSERT/WARNING from package ieee.STD_LOGIC_ARITH, Built-in function result set to 'X' due to a ('U', 'X', 'W', 'Z', '-') in an operand / Built-in function CONV_INTEGER/TO_INTEGER argument too large Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0! (ModelSim, VHDL Output File (.vho))LPM_MUX, LPM_ADD_SUB, LPM_COMPARE, and LPM_CONSTANT IP cores not enabled for Arria 10 and Stratix 10 devices in Quartus Prime.
Description Quartus Prime software generates the following compilation error when either LPM_MUX, LPM_ADD_SUB, LPM_COMPARE, or LPM_CONSTANT IP cores is compiled with Arria 10 and Stratix 10 in Quartus Prime Pro edition because these IP cores are not enabled for these devices: Error(18185): Your design contains IP components that must be regenerated. To regenerate your IP, use the Upgrade IP Components dialog box, available on the Project menu in the Quartus Prime software Error(18186): You must upgrade the IP component instantiated in file mymux.v to the latest version of the IP component. Error: Flow failed: ERROR: Current design not found Resolution To avoid the compilation error, remove the .qip file of the instantiated IP cores from your Quartus project. Include only the .v or .vhdl files of the instantiated IP cores into your Quartus project. This issue will be fixed in future releases.Why do I get a VHDL Use Clause error in Quartus II when compiling a VHDL file generated by DSP Builder?
Description You will get a VHDL Use Clause error in Quartus II when compiling a VHDL file generated by DSP Builder if you have not added the appropriate DSP Builder library files to your Quartus II project. These library files should already be added to the project for you if you run Quartus II from within SignalCompiler or if you use the Quartus II tcl script generated by DSP Builder. However, if you are running the Quartus II compile outside of SignalCompiler and are not using the Quartus II tcl script, you will need to set these library files up manually. The text of the error will look similar to: Error: VHDL Use Clause error at <filename>.vhd: design library does not contain primary unit dspbuilder block Error: Ignored construct <entity name> at <filename>.vhd because of previous errors To compile DSP Builder generated VHDL files in Quartus II, you must have the path to the DSPBUILDERPACK.vhd and DSPBUILDER.vhd files specified in your Quartus II project. These files are located in the <DSP Builder install directory>\altlib directory. To add these files, select Add/Remove Files in Project... under the Project menu in Quartus II. Browse to the <DSP Builder install directory>\altlib directory and select the DSPBUILDERPACK.vhd and DSPBUILDER.vhd files and click OK to add the files. The compilation order of the files is important. DSPBUILDERPACK.vhd must be compiled before DSPBUILDER.vhd. Once you have included the files, rerun your Quartus II compile.Why are there seed dependent functional failures where the registers feeding into and from DSP blocks stuck in reset status when compiled in the Intel® Quartus® Prime Pro Edition Software v20.1?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v20.1, you might observe the registers surrounding DSP blocks stuck in reset status even after reset removal. This error might be seen on the Intel® Stratix® 10 and Intel Agilex® 7 devices. This is due to a DSP unpacking problem that is causing registers being created with incorrect reset polarity. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software v20.2. If you are still in the design phase of your project, and are using the Intel® Quartus® Prime Pro Edition Software v20.1 or earlier, but cannot move to the latest version: Download and install the Solution Patch from the given link below. Recompile your design with the Solution Patch installed. If you are targeting the Intel® Quartus® Prime Pro Edition Software v20.1 or earlier, and your project is finalized and in the production phase, follow steps 1 to 3 for an impact assessment on each individual compilation: Download and install the Screening Patch from the given link below. Recompile your design with the Screening Patch installed. a. If your design is affected, you will see the following warning in the Intel Quartus software compilation flow message window. Proceed with step 3. Warning (22057): Screening patch found a case where the DSP Register Unpacking might create incorrect logic. Install the solution patch to fix the issue, available in the knowledge database solution: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2020/why-are-there-function-failures-in-some-seeds-while-there-are-no.html b. If the above warning is not reported, no further action is required. 3. Download and install the Solution Patch from the given link below. Recompile your design with the Solution Patch installed. Screening Patch: Intel® Quartus® Prime Pro Edition Software version 20.1 Screening Patch 0.52 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software version 20.1 Screening Patch 0.52 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software version 20.1 Screening Patch 0.52 (.txt) Solution Patch: Intel® Quartus® Prime Pro Edition Software version 20.1 Solution Patch 0.32 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software version 20.1 Solution Patch 0.32 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software version 20.1 Solution Patch 0.32 (.txt) Note: Caution: Patch installation sequence for Screening Patch and Solution Patch matters – the latest installed patch overrides the previous patch. Do not install the screening patch after installing the solution patch. Ensure that ONLY the Screening Patch is installed during the screening step. You may then install the solution patch on top of the Screening Patch once your screening step is completed with specific warning messages reported. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software v20.2.Where can I find the Fin Actuator design example in the Hardware In The Loop Whitepaper?
Description The following whitepaper mentions a fin actuator example design, but there are no instructions on where to find it: http://www.altera.com/literature/wp/wp-01208-hardware-in-the-loop.pdf Resolution The attached zip file has the fin actuator example discussed in the whitepaper. Fin Actuator Example