Chainin and Chainout Ports in Arria 10 Native Fixed Point DSP IP Core Not Supported for m18x18_full Operation Mode.
Description When the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, the chainin and chainout ports are visible to users. However, these ports are disabled internally in m18x18_full operation mode. If you connect the chainin and chainout ports when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, there will be no data transfer in and out to the DSP core. Resolution Leave the chainin and chainout ports unconnected when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode. This issue will be fixed in a future version of the Quartus II software.Tcl error: can't read "library_path": no such variable when compiling in DSP Builder?
Description In Altera® DSP Builder 8.1, the MegaWizard® purges files related to the MegaCore® whether or not any changes are made to the settings of the core. This includes simply verifying the parameters of a MegaCore block. This problem affects all MegaCore blocks in DSP Builder 8.1. The work around for this error is ensuring that if any MegaCore block is open in the MegaWizard, that the Generate button is pushed rather than just closing the MegaWizard window. This problem has been fixed in future versions of DSP Builder.Why is my Native Fixed Point DSP block showing an unexpected latency in simulation?
Description For some combinations of parameters, simulators and RTL coding styles, the latency of this block in simulation deviates from the expected latency by , - one clock. Actual hardware exhibits the expected latency. This behavior will be seen, for example, if the clock driving the DSP block is a delayed version of the clock generating the input data, thus introducing more simulation delay for the input clock than for the input data. Resolution To work around this problem, you must ensure that delays between the clock that generates input data to the DSP block, and the input clock of the DSP block, are balanced by delays on the input data. Alternatively ensure that the input data arrives at a later absolute time, or a later simulation delta delay time, compared to the input clock of the DSP block. Note that such things as more assignment statements on the clock path vs. the data path will cause simulation delta delay differences between those paths. To accomplish this, modify your testbench to: Ensure the clock generating inputs to the Native DSP block is exactly the same signal as the clock input to the Native DSP block. If #1 is not feasible, delay the input data relative to the clock. For example, consider the following original RTL code: Original RTL: clk_gen: process begin clk_orig <= \'0\'; wait for 5 ns; clk_orig <= \'1\'; wait for 5 ns; end process; ... if (rising_edge(clk_orig)) then ax <= ax 1; ay <= ay - 1; end if mac_test_bad_style: mult_acc port map ( ... ax => std_logic_vector(ax), -- [in] ay => std_logic_vector(ay), -- [in] clk => ("00" & clk_orig), -- [in] resulta => resulta2, -- [out] ... ); resulta2 will show one clock less latency than expected. Note that the concatenation of "00 & clk" in the multiplier\'s clk port assignment adds a simulation delta delay from the "clk_orig" which generates the input data. Possible workarounds include: Example 1, Recommendation: Use a 3-bit clock throughout You can generate the multiplier\'s 3-bit clock directly and use the active bit to clock the input data: clk_gen: process begin clk3bit <= \'000\'; wait for 5 ns; clk3bit <= \'001\'; wait for 5 ns; end process; ... if (rising_edge(clk3bit(0))) then ax <= ax 1; ay <= ay - 1; end if mac_test_bad_style: mult_acc port map ( ... ax => std_logic_vector(ax), -- [in] ay => std_logic_vector(ay), -- [in] clk => (clk_3bit), -- [in] resulta => resulta2, -- [out] ... ); Example 2, Alternate Recommendation: add corresponding delay to the input data The \'clk => ("00" & clk_orig)\' statement causes the \'clk" port to have an additional simulation delta delay from \'clk_orig\' that\'s driving the data. To overcome this, you can use the original clk_gen process and just add simulation delta delays to the data with assignment statements. clk_gen: process (same as original) ax_del <= ax; ay_del<=ay; mac_test_bad_style: mult_acc port map ( ... ax => std_logic_vector(ax_del), -- [in] ay => std_logic_vector(ay_del), -- [in] clk => ("00" & clk_orig), -- [in] resulta => resulta2, -- [out] ... );How do I specify which registers to use within the Stratix digital signal processing (DSP) block?
Description The three sets of registers within the DSP block are input registers, pipeline registers (output of multiplier unit), and output registers. If you are implementing the simple multiplier mode and using the LPM_MULT function, you can set the LPM_PIPELINE parameter to 1, 2, or 3. When set to 1, it uses the input registers. When set to 2, it uses the pipeline registers. When set to 3, it uses all 3 input, pipeline, and output registers. For the other modes, the ALTMULT_ADD and ALTMULT_ACCUM functions have these registers specified explicitly in the MegaWizard ® Plug-In Manager. If you want to use just the input and output registers (bypass the pipeline registers) in the simple multiplier mode, you can use the ALTMULT_ADD function, implement an independent multiplier by setting the NUMBER_OF_MULTIPLIER parameter to 1, and then explicitly specifying the appropriate register stages.Why does the Avalon® streaming interface of my DSP Builder for Intel® FPGAs component fail to connect in Platform Designer?
Description Due to a problem in DSP Builder for Intel® FPGAs version 20.3 and earlier, you may see that the Avalon® streaming interfaces of your DSP Builder for Intel® FPGAs component fails in Platform Designer. This problem occurs when you have selected single conduit generation in DSP builder for Intel® FPGAs. The ports for the Avalon® streaming interface ports are not written to the hw.tcl file. Resolution To work around this problem, select multiple conduit generation in DSP Builder for Intel® FPGAs or add the missing ports to the hw.tcl file manually. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.4.Why does the MATLAB* Help Window not open, show a blank window, or give a “No Internet Connection” error when I click on the Help icon inside DSP builder
Description The MATLAB* Help Window might not display the documentation content properly even when the computer has internet access. The user might experience the same issue when clicking on the MATLAB Help icon within the DSP Builder tool. Possible failure modes include: The Help link does not open a window at all. The Help content does not load and only shows a blank page. The "No Internet Connection" message is shown. Resolution Please take a look at the MATLAB web version documentation. For the MATLAB version R2021a - https://ww2.mathworks.cn/help/releases/R2021a/documentation-center.html For the MATLAB version R2021b - https://ww2.mathworks.cn/help/releases/R2021b/documentation-center.html For the MATLAB version R2022a - https://ww2.mathworks.cn/help/releases/R2022a/documentation-center.html For the MATLAB version R2022b - https://ww2.mathworks.cn/help/releases/R2022b/index.html For the MATLAB version R2023a - https://ww2.mathworks.cn/help/releases/R2023a/index.html For the MATLAB version R2023b - https://ww2.mathworks.cn/help/releases/R2023b/index.html For the MATLAB version R2024a - https://ww2.mathworks.cn/help/releases/R2024a/index.html For the latest MATLAB version - https://ww2.mathworks.cn/help/index.htmlWhy does DSP builder advance synthesisInfo block fail to constrain the latency when it is specified?
Description When using the synthesisInfo block in the DSP Builder Advanced library, the latency can only be constrained between the ChannelIn and ChannelOut block. Resolution If you are using GPIN and GPOUT bock as an interface to your subsystem, the synthesisInfo block latency constraint will not be taken into account, unless they are replaced by a pair of ChannelIn and ChannelOut block.Can I mix multipliers of different widths in the same Stratix digital signal processing (DSP) block?
Description Yes. You can place multipliers with an input width greater than 9 bits and less than or equal to 18 bits together in a DSP block, as the block will operate in 18×18 mode. You can also place multipliers with an input width less than or equal to 9 bits together in a DSP block, where the block operates in 9×9 mode. For example, a 16×16 and 18×18 multiplier can share the same DSP block as well as a 4×4 and an 8×8 multiplier. Since a DSP block can operate in only one mode at a time, it is not be possible to have both types of multipliers in the same DSP block. You can convert a smaller multiplier (less than or equal to 9 bits) to be implemented in an 18×18 mode by extending the input width to at least 10 bits.Why is there no "Clear Type" parameter in the Native Floating-Point DSP Intel® Arria® 10 FPGA IP?
Description Due to a problem with the Native Floating-Point DSP Intel® Arria® 10 FPGA IP Core User Guide, the "Clear Type" parameter is incorrectly shown as supported. The Native Floating-Point DSP Intel® Arria® 10 FPGA IP does not support the "Clear Type" parameter. Resolution This problem will be fixed in a future version of the Native Floating-Point DSP Intel® Arria® 10 FPGA IP Core User Guide.Can I have operands with different signs feeding the multipliers in Stratix devices?
Description Yes. There are two separate digital signal processing (DSP) block sign control signals: "Sign A" and "Sign B." A logical 1 on the sign control signal indicates that the operand is a signed number. The result of the multiplication will be a signed number if any one of the operands is a signed number. The Sign A and Sign B signals affect the entire DSP block. Therefore, all the Data A inputs feeding into the same DSP block must have the same sign representation. Similarly, all the Data B inputs feeding into the same DSP block must have the same sign representation. By default, the DSP block will implement signed multiplication.