Why do I get a fatal error when I have a wildcard in my Nodefinder search?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1 and earlier, you might see a fatal error when searching in the Nodefinder launched from the Signal Tap Logic Analyzer. The error mostly occurs when the Nodefinder searches for a wildcard in the Named path at the hierarchy level where an encrypted IP is instantiated. Resolution This problem has been fixed beginning with the Quartus® Prime Pro Edition software version 25.1.1.What are the valid bits of the reconfiguration address bus to specify the selected channel when enabling the "Share reconfiguration Interface" option for the Transceiver Native PHY Arria® 10 FPGA/Cyclone® 10 GX FPGA IP
Description Due to a problem in the Transceiver Native PHY Arria® 10 FPGA/Cyclone® 10 GX FPGA IP information window, when enabling the "Share reconfiguration Interface" option, there is an incorrect message that upper[n:9] address bits of the reconfiguration address bus specifies the selected channel. According to the Arria® 10 Transceiver PHY User Guide, when you turn on the "Share reconfiguration Interface" option, the Transceiver Native PHY IP presents a single Avalon memory-mapped interface slave interface for dynamic reconfiguration for all channels. In this configuration, the upper [N-1:10] bits of the reconfiguration address bus specify the selected channel. The channel numbers N are binary encoded. Address bits [9:0] provide the register offset address within the reconfiguration space for a channel. Resolution
Why does the SPI (4 Wire Serial) IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see hold timing violations during Timing Analyzer when using the SPI (4 Wire Serial) IP. The SPI IP generates an SDC file that includes the following incorrect constraint: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] This constraint can cause hold timing violations between the spi_gen_clk and the external clock, making timing closure difficult—especially in designs with multiple SPI instances. This problem does not occur in the Quartus® Prime Standard Edition Software, where such an SDC constraint is not generated for the SPI IP. Resolution To work around this problem: Remove the incorrect constraint from the IP-generated SDC file: Delete the following line: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Internal Error: Sub-system: RDB, File: /quartus/db/rdb/rdb_utility.cpp, Line: 1944 rval == nullptr
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see this internal error when performing an IP Upgrade. Resolution To work around this problem, delete the qdb folder before compiling the project. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Error(24244): Found an error when generating the IBIS Output File for board analysis
Description Due to a problem is Quartus® Prime Pro Edition Software version 25.3, you might see this error when generating this IBIS files. This problem only occurs on Windows* OS. This problem occurs because the quartus_py.exe file has changed location in the installation directory but the IBIS writer still calls the file from the previous location. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why does the DisplayPort example design fail to generate in Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see a software build failure when generating the DisplayPort FPGA IP Design Example. In this condition, the generated Nios® V software build fails in debug.c because the load_resolutions() call passes modes_found instead of &modes_found. You may see an error similar to the following: debug.c:486:94: error: passing argument 4 of 'load_resolutions' makes pointer from integer without a cast note: expected 'int *' but argument is of type 'int' Error: Failed to generate example design Resolution To work around this problem, modify debug.c line 486 either in the installed source or in the generated example design, and then regenerate or rebuild the design. Change: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, modes_found); to: load_resolutions (1, mode_param_array, &dsc_data_pps_parameters, &modes_found); This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Error: add_fileset_file: No such file C:/intelFPGA_pro/21.1/ip/altera/sld/st/intel_st_debug_if/cadence/intel_st_dbg_if_csr_h.sv
Description Due to a problem in the JTAG-Over-Protocol Intel® FPGA IP, using the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2 you may see an error message similar to the following when generating the HDL code with the option Create simulation model= Verilog or VHDL. Error: add_fileset_file: No such file C:/intelFPGA_pro/21.1/ip/altera/sld/st/intel_st_debug_if/cadence/intel_st_dbg_if_csr_h.sv while executing "add_fileset_file $current_sim/intel_st_dbg_if_csr_h.sv SYSTEM_VERILOG PATH $current_sim/intel_st_dbg_if_csr_h.sv $attr" (procedure "add_rtl_files" line 25) invoked from within "add_rtl_files sim" (procedure "sim_callback" line 2) invoked from within "sim_callback intel_st_dbg_if_top" Resolution A patch is available to work around this problem for the Intel® Quartus® Prime Pro Edition Software version 21.1 and 21.2. Download and install the patch from the appropriate link below. Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 for Windows (.exe) Download patch Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition 21.1 Patch 0.40 (.txt) Download patch Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 for Windows (.exe) Download patch Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition 21.2 Patch 0.13 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.When using the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI* Express Avalon-ST, why is the host system unable to detect the PCIe link or fail to boot up from BIOS?
Description Due to a problem with the Intel® Quartus® Prime Pro Edition software version 19.3, you may encounter the above problem, this is due to an incorrect implementation of the pld_clk_inuse signal of the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI* Express. Resolution A patch is available to fix this problem. Download and install patch 0.26 for Intel® Quartus® Prime Pro Edition software version 19.3. Download patch 0.26 for Windows* (quartus-19.3-0.26-windows.exe) Download patch 0.26 for Linux* (quartus-19.3-0.26-linux.run) Download the Readme for patch 0.26 (quartus-19.3-0.26-readme.txt) This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.4.