CXL Adoption Ramps with New Product Announcements from Intel and Others
Enthusiasm over Artificial Intelligence (AI) related products, such as the generative AI software ChatGPT, is igniting another wave of demand for high-performance computing, and a return to typical growth patterns in data center infrastructure, cloud computing, and high-performance computing (HPC) segments.
CXL IP Debug Toolkit
Hello, An Intel development kit DK-DEV-AGI027R1BES with the CXL Type 3 Example Design image causes an AMD Siena architecture system to reboot when a single write is issued. The information extracted by the Debug Toolkit seems to point to failures, but the documentation does not give details on the description of the registers. The most notable entries are: Local Retry State Machine,0x8c00 Num Local CRC Detected,0x2 Local FSM State Status,0x3 Viral Log,0x4 Link Received Viral,0x1 BBS Idle Status,0x0 BBS Error Status,0x1 BBS CXL Status Register Slice0,0xc0000000 BBS Error Status Register,0x12 Device Protocol Table Error,0x1 M2S Viral Received,0x1 BBS Error Status First Register,0x10 The counters show some interesting results. Even though a single Byte RwD was requested by the application, a Req also happened, and apparently only the Req was responded with DRS, whereas the RwD didn't trigger NDR to be sent: Counter of M2SReq Operations,0x1 M2SReq Counter,0x1 Counter of M2SRwD Operations,0x1 M2SRwD Counter,0x1 Counter of S2MDRS Operations,0x1 S2MDRS Counter,0x1 Counter of S2MNDR Operations,0x0 S2MNDR Counter,0x0 Is there more information available on the meaning of the registers for the CXL IP Debug Toolkit? Thank you, Ricardo PS: The complete dump of registers from the Debug Toolkit can be found attached.CXL Type 3 Design Example 1.81 simulation issue
Hi, The version 1.81 of the Design Example of the CXL Type 3, using Quartus 23.1 source files, does not behave as intended. The testbench supposedly issues MemWrites of 1500 cache lines, and reads them back for consistency checking. However, an apparent issue in the encrypted macro `CXL_TB_DO_BBS_BUSY_CHECKS (line 187 of tb/tests/cxl_base_test.sv) causes the testbench to stop the MemWrites at packet 1458, which leads to the failure of execution of the next phase, the MemReads. As a test, I modified the testbench not to use the failing macro, and that assisted the simulation to finish the MemWrites. However, the following error happened during the first read transaction: "/quartus/hyb-type3/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_180/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: started at 512100001423fs failed at 512100001423fs Offending '<Protected>' Error: "/quartus/hyb-type3/intel_rtile_cxl_top_0_ed/intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_180/sim/dcc_top.sv", 23: cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.PROTECTED.dcc_ptM2SReq_illegal_asrt: at time 512100001423 fs >>>> Time=512100.001ns, ASSERT - DCC M2SReq PT illegal asserted >>>> Op=M2SREQDCD_RSVD31, ReIssue=0, Hit=0, CurrSt=TAGSTATE_I, NxtSt=TAGSTATE_ILLEGAL As a reference, the 1.7 version of the Design Example using the Quartus 22.4 source code works correctly. I have attached the simulation log files from the original run, and from the modified one. Thank you, Ricardo
CXL type 3 example design increase to 128GB per channel?
What needs to change in the CXL type 3 example design to increase the Memory to 128GB per channel? I tried changing the emif IP to a DIMM, and updated the scripts to not define ENABLE_DDR_DBI_PINS. I updated the pinouts. But I get: Error(129015): Output port DATA_OUT on atom "ed_top_wrapper_typ3_inst|MC_CHANNEL_INST[0].mc_top|GEN_CHAN_COUNT_EMIF[0].emif_inst|emif|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[2].lane_inst|lane_inst", which is a tennm_io_12_lane primitive, is not legally connected and/or configured Info(129016): Output port DATA_OUT[8] is disconnected, but the Compiler expects this output port to be connected Any idea what I am missing?
Request for an official email to declare Intel acquired structured eASIC company.
Our company want to send an quotation to eASIC company before, but found that Intel acquired structured ASIC company eASIC into Programmable Systems Group (PSG). Could you please send us an official email to declare this situation for our record, thank you.
Inquiry about Device Compatibility and Version Support for AGIB027R29A1E2VR3 in Quartus Prime Pro V
During the New Project stage, the device model AGIB027R29A1E2VR3 is not available, but the Development Kit DK-DEV-AGI027R1BES is present. However, in the device model list, AGIB027R29A1E2VRC is found. Are VRC and VR3 the same device? Or is it that version 24.2 does not support the device AGIB027R29A1E2VR3? OS: Windows11 Quartus version:24.2
