Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory (Case 1) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off Enable SPI pins interface is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Active Serial configuration flash memory (Case 2) Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned on Connected to a SFL IP with Share ASMI interface with your design option turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Enable SPI pins interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why do the Quartus II in-system debugging tools fail to work properly with my Arria II GZ device?
Description Due to a problem in the Quartus® II software versions 11.0 and earlier, Quartus II in-system debugging tools may fail to work correctly with certain Arria® II GZ devices. This problem may affect the following debugging tools that use the JTAG chain to communicate to the device: The SignalTap™ II Logic Analyzer The Logic Analyzer Interface The In-System Memory Content Editor The In-System Sources and Probes System Console utilities A patch is available to fix this problem for the Quartus II software versions 11.0 and 10.1 SP1. Download and install the appropriate patch from the links below: Quartus II software version 11.0: Download the version 11.0 patch 0.07 for Windows (.exe) Download the version 11.0 patch 0.07 for Linux (.tar) Download the Readme for the Quartus II software version 11.0 patch 0.07 (.txt) Quartus II software version 10.1 SP1: Download the version 10.1 SP1 patch 1.73 for Windows (.exe) Download the version 10.1 SP1 patch 1.73 for Linux (.tar) Download the Readme for the Quartus II software version 10.1 SP1 patch 1.73 (.txt) This problem is fixed beginning with the Quartus II software version 11.0 SP1.Error (21216): Cannot enable error detection cyclic redundancy check without instantiating the ALTERA_CRCERROR_VERIFY megafunction.
Description The EDCRC false error known issue found in Stratix® IV device and Arria® II device families require instantiation of an Altera CRCERROR Verify v12.0 megafunction. However, the Altera CRCERROR Verify v12.0 megafunction is not available in the Quartus® II software version 12.0. During compilation of a design that uses the error detection CRC feature, the Quartus II software reports above error. Resolution Refer to the Stratix IV device and Arria II device families errata sheet for the details on this EDCRC false error known issue. If you require the Altera CRCERROR Verify v12.0 megafunction for the EDCRC false error solution in the Quartus II software version 12.0, install patch 0.04 from the following links: Download the Quartus II software version 12.0 Patch 0.04 for Windows (.exe) Download the Quartus II software version 12.0 Patch 0.04 for Linux (.tar) Readme for the Quartus II software version 12.0 Patch 0.04 for Linux (.txt) This issue is scheduled to be fixed in a future version of the Quartus II software. Related Articles Error (21217): ALTERA_CRCERROR_VERIFY megafunction is not instantiated for stratixiv_crcblock primitive instance crcblock_componentWhy is the PCIe Gen2 link for Arria II GZ transceivers not getting established?
Description Arria® II GZ transceivers configured in PCIe Gen2 mode may have link bring-up issues due to a software bug in Quartus® II software version10.1. For additional details, you can refer to the Arria II GZ Errata Sheet (PDF). You can install the following patches to resolve this issue for the Quartus II software version 10.1 or 10.1 sp1. Download the Quartus II software version 10.1 Patch 0.11 for Windows (.exe) Download the Quartus II software version 10.1 Patch 0.11 for Linux (.tar) Download the Readme for the Quartus II software version 10.1 Patch 0.11 (.txt) Download the version 10.1 sp1 Patch 1.11 for Windows (.exe) Download the version 10.1 sp1 Patch 1.11 for Linux (.tar) Download the Readme for the Quartus II software version 10.1 sp1 Patch 1.11 (.txt) This issue will be fixed in future software version. Note: Arria II GZ is not supported in 9.1 SP2 and earlier software.Does the ALTASMI_PARALLEL megafunction support execution of the 4BYTEADDREX instruction for EPCQ256 configuration devices?
Description In the Quartus® II software version 13.0 SP1 and earlier, the ALTASMI_PARALLEL megafunction does not provide a way to issue the 4BYTEADDREX instruction to an EPCQ256 configuration device. This instruction is required to exit 4-byte addressing mode once it has been entered via the 4BYTEADDREN instruction. This is important only if using an Altera® device family older than the 28-nm generation (like Stratix® IV devices) to configure from an EPCQ256 configuration device. Device families older than 28-nm require the EPCQ256 configuration device to be in 3-Byte addressing mode to configure successfully. Resolution The following patch for the Quartus II software version 13.0 adds a port to the ALTASMI_PARALLEL megafunction that facilitates execution of the 4BYTEADDREX instruction. Download the version 13.0 patch 0.37 for Windows (.exe) Download the version 13.0 patch 0.37 for Linux (.run) Download the Readme for the Quartus II software version 13.0 patch 0.37 (.txt) This function is scheduled to be incorporated in a future verison of the Quartus II software.Why assertion of reset may cause low probablity lock up of UniPHY NIOS sequencer resulting in incomplete calibration
Description UniPHY IP does not complete calibration after asserting and deasserting global_reset_n or soft_reset_n signal low for UniPHY IP. EMIF debug toolkit cannot be connected to that interface (link project to device). This condition does not change even if multiple resets are issued later. This condition can be recovered only by reconfiguring the device. These symptoms can be caused by the internal reset structure of the EMIF UniPHY IP. An asynchronous reset assertion to the logic driving the address bus of an M20K RAM can cause asynchronous logic propagation. This can impact functionality of M20K address row/column decoders, opening more than one word line which can result in charge sharing between bit cells, corrupting the contents of the M20K. Note that the probability of M20K corruption due to asynchronous reset assertion is very low. PLL reset during M20k read or write operation can also contribute to embedded RAM/ROM corruption because PLL lock loss may result in a clock glitch during reset and this may impact the functionality of M20K address row/column decoders. This corruption affects the UniPHY IP because it contains a Nios (R) II processor that is used for calibration, and the processor's program code is stored in M20K RAM. If the corruption occurs within the Nios (R) II program memory, this can cause the Nios (R) II sequencer to lock up, resulting in incomplete calibration. Recovery from this situation is only possible by reprogramming the device, as M20K contents are only loaded during device programming. It is important to note that common EMIF failures listed below does not necessarily mean the M20K RAM is corrupted or Nios (R) II sequencer is locked up - If calibration never passes (i.e. calibration always fails). - If calibration margins are very slim, and occasionally fail calibration. - If design passed calibration, and occasional data errors are observed while running the design. - If design says it passed calibration, but design is not working as expected. Resolution UniPHY IP core has two reset inputs Global_reset_n: is connected to everything in UniPHY IP including PLL. Soft_reset_n: is connected to everything in UniPHY IP except PLL. 1. Altera strongly recommends using only soft_reset_n at all times. Use global_reset_n only for Power on reset. To reset PLL during Power on, Use the following sequence a. Assert Global_reset_n (PLL reset ) b. Power up and reconfigure the chip c. De-assert Global_reset_n 2. The fix changes the internal reset controller and reset structure of the UNIPHY IP core to use synchronous resets, as well as pre-emptively deasserting the M20K clock_enable port during a reset condition. This prevents any metastable transitions from propagating into the M20K address decoder. This fix will be provided as part of 13.0dp1, 13.0sp1, and all subsequent versions of Quartus. Users will need to regenerate the UnipHY IP and recompile the design. Altera recommends moving to one of these versions of Quartus. If a fix is required more urgently, or a fix is required for Quartus version 12.1sp1, the UniPHY IP core can be manually updated. The following procedure must be followed: Locate the source files for the Altera UniPHY IP within your design. There are 5 files that need to be modified. altera_reset_synchronizer.v altera_reset_controller.v altera_mem_if_sequencer_mem_no_ifdef_params.sv <interface_name>_if0_p0_reset.v <interface_name>_if0_s0.v Steps 1. Download altera-reset-synchronizer.v from the following link and place in the same directory as the UniPHY IP source files: Altera_reset_synchronizer.v 2. Download altera-reset-controller.v from the following link and place in the same directory as the UniPHY IP source files: Altera_reset_controller.v 3. In altera_mem_if_sequencer_mem_no_ifdef_params.sv’ – Ensure that the input ‘s1_clken’ connects to the ‘clocken0’ input of the ‘the_altsyncram’ 4. In instance<interface_name>_if0_p0_reset.v – modify the defparam statements for the “dut_if0_p0_reset_sync” instances so that the parameters “RESET_SYNC_STAGES” and “NUM_RESET_OUTPUT” are set according to the attached sample file (dut_if0_p0_reset.v). (Do not download the sample file in the UniPHY IP source file directory) dut-if0-p0-reset.v (sample file for <interface_name_if0_p0_reset.v) 5. In <interface_name>_if0_s0.v (Do not download the sample file dut_if0_s0.v in the UniPHY IP source file directory) dut-if0-s0.v (sample file for <interface_name>_if0_s0.v ) – Add the following port to the top level: wire early_rst_controller_reset_out_reset; - Wire the output port “m20k_gate” on the “rst_controller” module to the ‘s1_clken’ input of ‘sequencer_mem’ module. Since the M20k_gate output is active-low, you need to invert the output as follows: .s1_clken (~early_rst_controller_reset_out_reset), // on sequencer_mem, line 785 of the attached sample file (dut_if0_s0.v) .m20k_gate (early_rst_controller_reset_out_reset), // on rst_controller, line 2572 of the attached sample file 6. Once these changes have been made, your design will need to be recompiled. Related Articles How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0? Why does the Qsys on-chip memory (RAM or ROM) content get corrupted after asynchronous reset?Why does my PCIe link get stucked in the Detect state for Arria® II and Stratix® IV devices?
Description Due to a problem in the PCIe Hard IP PMA, the link may get stucked in the Detect.Active state. This is because the transceiver receiver detect logic not returning a PHYSTATUS pulse on the PIPE interface to the Hard IP core if the low period of two consecutive TxDetectRx is less than 544 ns. This problem affects Stratix® IV GX, Stratix® IV GT, and Arria® II GX devices. Resolution Manually change the Hard IP reset logic to assert the crst and srst signal for at least 1 us. You can use the following files to view the changes required for both Avalon® streaming and Avalon® memory mapped interfaces to satisfy the requirement above. top_rs_hip (.v): Added reset logic can be found on lines 181-211. Put these lines in your <instantiation name>_rs_hip.v file for Avalon streaming interfaces. pcie_compiler_0 (.v) : Added reset logic can be found on lines 648-684. Put these lines in your instantiation file for Avalon memory mapped interfaces. pcie_compiler_0 (.vhd): Added reset logic can be found on lines 775-810. Put these lines in your instantiation file for Avalon memory mapped interfaces. Related Articles Why does my PCIe link get stuck in the Detect state for the SOPC Builder Avalon-MM Cyclone IV device?SPI Slave to Avalon Master Bridge data loss
Description Due to a problem in the Quartus® II software, the SPI Slave to Avalon® Master Bridge IP, may drop data under heavy load. Resolution To workaround this problem, replace the generated synthesis/submodules/spiphyslave.v file with this file: spiphyslave.vWhy does my Deinterlacer II license fail?
Description Due to a problem in the Quartus® Prime Standard edition software version 16.1, designs containing the Deinterlacer II IP only generate a time-limited programming file. Resolution To resolve this problem in the Quartus Prime Standard edition software version 16.1, download and install the patch from the links below: Download the Quartus Prime version 16.1 Patch 0.04 for Linux (.run) Download the Quartus Prime version 16.1 Patch 0.04 for Windows (.exe) Download the Quartus Prime version 16.1 Patch 0.04 Readme (.txt) This problem is scheduled to be fixed in a future release.