Why does my Quartus® Prime Installation fail with certificate error: SSL certificate problem: unable to get local issuer certificate (curlcode 60)?
Description Due to a problem in the Quartus® Prime Installer Software, you might see the error message shown below when you click Download & Install. This happens because the certificate bundled with the Quartus® Prime Installer Software is no longer accepted by the Altera® Content Delivery Network (CDN). As a result, secure downloads initiated during the installation process cannot be verified using the outdated certificate. The issue impacts the Installer for the following versions of Quartus software: Operating System Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) Microsoft Windows* 23.3 to 25.3.1 23.1std to 25.1std Linux* 23.3 to 23.4 23.1std The KDB workaround provided below applies to the following versions of Quartus software: Quartus Prime Pro Installer Version(s) Quartus Std/Lite Installer Version(s) KDB workaround applies to 24.3 to 25.3.1 24.1std to 25.1std Note that for all other affected versions not covered by the KDB, you cannot use the installer workaround and must download Quartus software package files individually without using the installer. Separate packages can be found in the Individual Files tab of the Quartus Software Download pages. Resolution To work around this problem, follow these steps: 1. Download and unzip the cacert.zip, which contains the cacert.pem certificate file. 2. Specify the new certificate using one of the following methods: i) Command Line Interface (CLI): Open a command prompt or terminal and run the installer with the--cacert option, pointing to the new certificate file. Windows*: qinst_<version>.exe -sp"--cacert <full path to cacert.pem>" Linux*: qinst_<version>.run -- --cacert <full path to cacert.pem> ii) Graphical User Interface (GUI): - Open the Quartus® Prime Installer, navigate to Settings, locate the CA Certificate Path, and specify the full path to the cacert.pem certificate file. - Then, click Apply > OK. This problem is scheduled to be resolved in a future release of the Quartus® Prime Installer Software.Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.
Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Error : FLEXlm version of vendor daemon is too old
Description In the Questa* FPGA Edition simulator and Questa* FPGA Starter Edition simulator version 2024.1, you might see this error or the following error if you are using the MGCLD daemon v11.16.4 “Unable to checkout a license. Make sure your license file environment variable (SALT_LICENSE_SERVER, MGLS_LICENSE_FILE, LM_LICENSE_FILE) is set correctly” Resolution To avoid this error, upgrade to the Siemens* Flexlm (SALTD) daemon v11.19.5 Download the daemon from the download page There is a change to the Siemens* License in v11.19.5.0. If you’re running a floating license server for Siemens* licenses, manually change the VENDOR daemon line in the license file from mgcld to saltd, for example: VENDOR saltd <path to saltd> Note: Do not change any of the INCREMENT lines. Leave the INCREMENT lines with the original vendor daemon name (mgcld).Why does the PCIe core send Unsupported Request completion message to my first good MRD request?
Description If bit 1 of the PCI® Command Register (Memory Space Access Enable) in the Configuration Space is not set, the PCIe core responds to the first good MRd request with a Completion with Unsupported Request status. To fix this issue, please set Memory Space Access Enable bit of the PCIe Command Register to one. Related Articles Why does the PCIe core return Unsupported Request for Type0 Configuration Read request?Why do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.How to mitigate the security vulnerability in the Nios® II Command Shell utility?
Description Due to a problem in the Quartus ® Prime Standard and Lite Edition Software version 19.1 through 24.1, the Nios® II Command Shell utility included in the Quartus ® Prime Software for Windows* is vulnerable to a Current Working Directory (CWD) planting attack. The Linux* versions are not affected. Resolution To work around this problem, replace the “Nios II Command Shell.bat” Windows Batch File located in the <drive>:\<edition>\<version number>\nios2eds\, with the attached file below. This problem is fixed beginning with the Quartus® Prime Standard and Lite Edition Software version 25.1.What is the loopback mode supported by Altera PCIe Hard IP core?
Description PCIe ® Hard IP (HIP) core does not support Loopback Master, but it supports Loopback Slave via PCIe Reverse Parallel Loopback configuration as indicated in device Transceiver Architecture chapter. Arria ® II GX PCIe Loopback Stratix ® IV GX PCIe Loopback The following list describes the loopback sequence: 1. The PCIe HIP core enters Loopback state when RC asserts loopback bit (bit2 of symbol 5) in TS1/TS2 during Configuration.LinkWidth.Start state. Both EP and RC must follow the rules as defined in PCI Express Base specification. 2. After successfully entering Loopback state, the core automatically asserts tx_detectrxloopback=1 and txelecidle=0 as required by PIPE interface spec. This will instruct the Altera transceiver to route the data after the Rate Match FIFO in Receiver Channel PCS to the associated Transmitter Channel. The receive data will pass through the CDR, deserializer, 8b/10b decoder, Word Aligner, and Rate Match FIFO before looping back to the transmit side. The transmit data will pass through the Rate Match FIFO, 8b/10b encoder and serializer before being transmitted out. 3. The RC transmits 8b/10b encoded patterns to the EP receiver during loopback mode as required by PCI Express Base spec. It also needs to send SKIP OS to make sure the Rate Match FIFO does not overflow or underflow. Similarly SKIP OS's will be inserted by the Rate Match FIFO in the EP transmit direction as required. Therefore, the EP transmit monitor must take this into account when comparing the looped back transmit data with the original receive data. The loopback pattern cannot be PRBS data because it is not 8b/10b encoded PCIe data. 4. To guarantee that good data is received properly, AC coupling is needed between RC transmit pins and the EP receive pins. As per the PCIe CEM (Plug in board) specification, the AC Coupling capacitors are always on the board with the transmit device pins. If a tester is hooked up to our card that is plugged into the PCI-SIG Compliance Base Board (CBB) via coax cables and the CBB does not have AC Coupling capacitors, physical DC blocks must be added in line with the cables to provide the same effect. So either AC Coupling capacitors or physical DC blocks are required between each RC transmit and the EP receive pin. 5. The system reference clock on the RC and EP must operate within /-300ppm according to PCIe spec. This is why the PCIe spec specifies that the loopback should pass through the Rate Match FIFO which can insert or delete SKIP OS's as needed to handle this range.How do I instantiate a differential input or output buffer in my design?
Description You can instantiate a differential input or output buffer in your design using the ALTIOBUF Intel® FPGA IP core available in the Intel® Quartus® Prime Software. Resolution The ALTIOBUF Intel® FPGA IP core allows you to specify your input or output pin as a differential receiver or transmitter and then you need to port both the positive and negative signals to I/O pins. This Intel FPGA IP core is supported beginning with the Stratix® III and Cyclone® III device families. For Stratix® II, Cyclone® II, Arria® GX, and previous device families, you cannot instantiate a differential buffer in your design. Instead, use the positive leg of the differential pair in your design, and locate that pin in the Assignment Editor. Give that pin an I/O standard assignment with a value of "LVDS" or the differential I/O standard you wish to use. Refer to the device handbook for a complete listing of the supported I/O standards. The negative leg will automatically be assigned to the corresponding complimentary pin by the fitter when you compile your design. This method is supported for all device families that support differential I/O standards such as LVDS. For more information on the ALTIOBUF Intel FPGA IP core, refer to the ALTIOBUF IP Core User Guide (PDF). Related Articles Internal Error: Sub-system: FIOMGR, File: /quartus/fitter/fiomgr/fiomgr_io_power_region.cpp, Line: 2460How much can I expect the solder balls of a BGA package to shrink after reflow?
Description You can expect the solder balls of a BGA package to shrink by about a third after reflow. For example, if the solder balls have a height of 0.3mm before reflow, they will shrink to a height of about 0.2mm after reflow.
