Why do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.How do I determine the phase shift and duty cycle for the required clocks if I am using ALTLVDS_RX and ALTLVDS_TX in external PLL mode?
Description You can determine the phase shift and duty cycle for the required clocks when using ALTLVDS_RX and ALTLVDS_TX in external PLL mode by first compiling an example design with ALTLVDS_RX or ALTLVDS_TX using an internal PLL. Use the settings that the Quartus® II software uses to configure the internal PLL in the example design as the settings you enter in the external PLL. To check the PLL settings in the Fitter report, expand the Resource section, and then expand PLL Usage. The report shows the duty cycle, phase shift and clock frequency for each of the required clocks for the ALTLVDS_RX and ALTLVDS_TX interfaces. You can then use these parameters for the external PLL settings in your design. Related Articles How do I implement ALTLVDS in External PLL Mode for Stratix V, Arria V, and Cyclone V devices? How do I implement the ALTLVDS_RX and ALTLVDS_TX megafunctions with External PLL mode in Arria II GX devices? How do you implement the altlvds megafunction with the External PLL option in Stratix III devices?Do I need to drive fftpts_in of the FFT Intel® FPGA IP core even if I'm not changing the block size?
Description You may receive source errors (missing SOP, missing EOP) when attempting to process data through the FFT Intel® FPGA IP core when fftpts_in not being driven or being driven incorrectly. Resolution fftpts_in must be driven, even if one is not dynamically changing the block size. For a fixed block size implementation, it should be driven to match the transform length selected in the parameter editor.Error (129036): Output port DATAOUT on atom "<slave DQS signal>", which is a arriav_delay_chain primitive, is not connected to a valid destination
Description This error may occur during synthesis when the afi_reset_n signal of a slave controller is not connected to the master controller's afi_reset_n output. Resolution Connect the afi_reset_n of the slave controller to the master controller\'s afi_reset_n output.Why do I get the following warnings during Analysis and Synthesis of Triple-Speed Ethernet (TSE) MegaCore design?
Description Warning (12189): OpenCore Simulation-Only Evaluation feature is turned on for all cores in the design Warning (12191): Some cores in this design do not support the OpenCore Plus Hardware Evaluation feature Warning (12192): ""Triple Speed Ethernet" (6AF7_0104)" does not support the OpenCore Plus Hardware Evaluation feature The warnings correspond to 'IEEE 1588v2 for Triple Speed Ethernet' feature added to the Triple-Speed Ethernet MegaCore ® (TSE). During Analysis and Synthesis, all TSE IP files are being compiled, including features not used, and thus the warnings are observed. Resolution The warnings can be safely ignored as they will not cause functional issues with the standard TSE features. The warnings will be removed in a future version of the Quartus ® II software.Where can I find the ALTMEMPHY and UniPHY IP tutorials and example design projects that were previously covered in the External Memory Interface Handbook?
Description For the 11.1 and later versions of the External Memory Interface Handbook, the ALTMEMPHY and UniPHY IP tutorials and example design projects have been moved to the FPGA wiki site (Intel Communities). Earlier versions of the External Memory Interface Handbook can be found on the External Memory Interface Handbook website under Related Documentation -> External Memory Interface.Why does the Generic Serial Flash Interface (GSFI) Intel® FPGA IP fail to write certain byte into the flash?
Description Due to the limitation in the Intel® Quartus® Prime Software version 19.1 and earlier, certain byte unable to write into the flash due to unsupported byteenable patterns/cases when the GSFI IP is connected to a 64-bit Avalon master and burst data transfer is being used. Below are the unsupported GSFI IP byteenable patterns/cases: 4'b0110 4'b0111 4'b1110 Resolution To work around this problem, either send data in 32-bit width or avoid using the unsupported byte enable patterns/cases. This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 20.1.What is the correct specification for pull-up and pull-down resistor values on JTAG pins (TMS, TDI, and TCK) for Altera FPGAs?
Description Altera recommends that you use pull-up resistor values between 1k and 10k ohms on the TMS and TDI pins and a pull-down resistor value of 1k ohms on the TCK pin. This recommendation applies to Cyclone®, Arria® GX, and Stratix® series devices.