The FIFO has no output waveform
Hi, I am currently using Quartus Prime Lite 24.1 and the 10M02M153C8G device to implement an 8Kx9 SYNC FIFO. I generated the design directly using the IP CORE. Initially, my tests successfully produced output waveforms. However, I must have changed a setting unintentionally, as I am now unable to simulate the output. Even previous projects that worked before are no longer producing any waveforms. I subsequently observed the following messages in the Simulation flow progress: Warning: sclr - signal not found in VCD. Warning: wrreq - signal not found in VCD. These warnings are appearing for multiple signals, as shown in the image or attachment (referring to the image/attachment). I have already tried reinstalling the software and updating the license options, but the issue persists. Could you please advise on the cause of this problem and how to resolve it? Thank you for your assistance.
Permission Denied issues with Questasim
Why am I getting errors when I compile that states "C:/Users/T/Documents/Quartus_Altera_Projects/concept/uvm_harness/src/sim/libraries/work\_dbcontainer\testbench_out\__mti.dbg". # Permission denied. (errno = EACCES)? When I get these errors, I have to restart Questasim.
quartus running the modelsim simulation failed
I am occuring a problem that i can't run the simulation of the wave, it always shows this error C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vsim -c -do lab01.do Error. GPT says that it happens because it can't operate the .do document when ModelSim is working, but i have tried many ways including reinstall everything but it still doesn't work. i really need someone to help me, thanks.Unable to use Avalon-MM master verification BFM in Questa sim
Hello, I have a bug similar to the one reported here : https://community.intel.com/t5/Intel-Quartus-Prime-Software/Avalon-Verification-IP-example-avlmm-1x1-vhdl-not-working-in/m-p/1516388 or here Unable to use Avalon-MM master verification BFM in Questa sim - Intel Community The Problem still exists in Questa 25.1 when using the "-suppress 12110" option it gives this warning: # ** Error (suppressible): (vsim-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases. Without using the "-suppress 12110" and the "-novopt" option all the Avalon BFM models won't work in Questa. Everything is running fine with modelsim. Are there any plans on fixing this issue? best regards FabianTiming Violations: 8x F-Tile ETH Hard IP TX_CLKOUT
Hello Intel Team, In our design, we instantiated eight 10G F-Tile Ethernet Hard IPs (including ANLT) using the VHDL "GENERATE" construct. During timing analysis, we are encountering setup and hold violations on the "TX_CLKOUT" path of the F-Tile transceivers. The "REPORT_CLOCKS" command shows that these 8 clocks are being generated with a frequency of 402.83 MHz under the following names: gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch23 gen_eth[1].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch22 ... gen_eth[7].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch16 The corresponding master clocks are: gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_pld_pcs_clk_reg|ch23 TX_CLKOUT clocks are asynchronous to each other and operate independently. Therefore, we attempted to exclude them from timing analysis using the "set_clock_groups -asynchronous" constraint, like this: set_clock_groups -asynchronous \ -group { [get_clocks {gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch23}] } \ -group { [get_clocks {gen_eth[1].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch22}] } \ -group { [get_clocks {gen_eth[2].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch21}] } \ -group { [get_clocks {gen_eth[3].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch20}] } \ -group { [get_clocks {gen_eth[4].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch19}] } \ -group { [get_clocks {gen_eth[5].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch18}] } \ -group { [get_clocks {gen_eth[6].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch17}] } \ -group { [get_clocks {gen_eth[7].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch16}] } However, this approach results in the following errors: - Warning(20314): Invalid collection filter: [get_clocks {gen_eth[0].proc...}] - Warning(332049): Ignored set_clocks_group: Argument -group with value could not match any element of the type clk. - Warning(332049): Argument -group is not an obejct ID. I’ve tried multiple approaches, get_nets, Get_pins, also using wildcards and "create_generated_clock", but nothing has resolved the issue. According to my understanding, a "create_generated_clock" constraint shouldn't be necessary, since these clocks are automatically generated by Quartus. When inspecting the design in the Timing Analyzer using "get_clocks *ch23, the clock names appear to be internally resolved to autogenerated IDs like "_co15660". However, these IDs are not stable and may change with each compile (fit), which makes them unsuitable for constraints. At this point, I am running out of ideas. Question: How can I properly constraint or eliminate the setup and hold violations on the eight "TX_CLKout" clocks generated by Quartus in the F-Tile Ethernet Hard IPs? Should I just use "Set_False_Path"? I used the "Generate" command in VHDL to instantiate the 8 F-Tile ETH Hard IP + 8 ANLT. Could be this a problem ? kind regards Jacob
'*.vho not found' in Modelsim ALTERA
Dear sirs, At QuartusII 13.1 / Stratix3 project, "DDR3 SDRAM Controller with UniPHY" IP on our design. I finished synthesys and run modelsim 10.1d for RTL simulation, After launched modelsim and do jobs in transcript window until 1st prompt. I got error: # vcom -93 -work work {*PATH*/*TO*/*PROJ/*IP_name*.vho} # Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012 # ** Error: (vcom-7) Failed to open design unit file "*PATH*/*TO*/*PROJ*/*IP_name*.vho" in read mode. Certainly do not have *.vho (IPFS FILES ?) file. How to generate it and run simulation?Simulation errors in Quartus generated simulation script for VCS tool
Hi All, Designed a platform with building blocks like HPS, OCM and HPS EMIF DDR. Executed the Quartus design simulation script for VCS tool. Encountered with errors regarding quartus internal encrypted files. Simulation Script: run_vcs="vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \ -l vcs_run.log \ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \ -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \ $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \ $QUARTUS_INSTALL_DIR/eda/sim_lib/tennm_atoms.sv \ $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/tennm_atoms_ncrypt.sv \ $QUARTUS_INSTALL_DIR/eda/sim_lib/fmica_atoms_ncrypt.sv \ $QUARTUS_INSTALL_DIR/eda/sim_lib/tennm_hssi_atoms.sv \ $QUARTUS_INSTALL_DIR/eda/sim_lib/tennm_hssi_atoms_ncrypt.sv \ $QUARTUS_INSTALL_DIR/eda/sim_lib/ctfb_hssi_atoms.sv \ $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/ctfb_hssi_atoms_ncrypt.sv \ $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/ctfb_hssi_atoms2_ncrypt.sv \ $QUARTUS_INSTALL_DIR/../devices/sim_lib/tennm_agilex7_io96.sv \ $QUARTUS_INSTALL_DIR/../devices/sim_lib/tennm_agilex7_io96_ncrypt.sv \ $common_design_files \ $design_files \ $USER_DEFINED_ELAB_OPTIONS_APPEND \ -top $TOP_LEVEL_NAME " Error Message: Parsing design file '/blrsim2/Tools/Intel/Quartus-pro-23_4/quartus//eda/sim_lib/synopsys/ctfb_hssi_atoms2_ncrypt.sv' Parsing design file '/blrsim2/Tools/Intel/Quartus-pro-23_4/quartus//../devices/sim_lib/tennm_agilex7_io96.sv' Parsing design file '/blrsim2/Tools/Intel/Quartus-pro-23_4/quartus//../devices/sim_lib/tennm_agilex7_io96_ncrypt.sv' Error-[PE_CDB] Corrupted data_block Checksum did not match for data_block in file '/blrsim2/Tools/Intel/Quartus-pro-23_4/quartus//../devices/sim_lib/tennm_agilex7_io96_ncrypt.sv' at line 5083314. CPU time: 268.274 seconds to compile Please support on this. BR Suresh
