Why is the o_rx_pfc port enabled for longer durations than normal when generating designs at 400G SIP using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates of 400G SIP with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the MAC TX of the F-Tile Ethernet FPGA Hard IP halt its transmission of control frames (0x8808) upon receiving PAUSE frames from the link partner?
Description According to Annex 31B.1 of the IEEE802.3 specification, it is noted that the pause operation does not inhibit the transmission of MAC control frames. However, the current implementation of the F-Tile Ethernet FPGA Hard IP mechanism for handling Ethernet frames is not aligned with this specification, as we pause the transmission of all Ethernet frames indiscriminately, regardless of their type. Users wishing to transmit PFC or SFC frames can utilize the SFC/PFC frame generation within HIP, facilitated by register configuration. It's important to note that while our system supports these specific frames, the IEEE specification includes a broader range of control frame types, as outlined in Annex 31A, which HIP does not generate. Alternatively, customers can configure the F-Tile Ethernet FPGA Hard IP to not halt traffic transmission upon receiving Pause frames. Instead, they can utilize the o_pause signal to make transmission decisions at the user end, particularly regarding the transmission of any control frames. Resolution There is no workaround for this problem.Why does the AXI-Lite interface read 'x' in simulation when attempting to access the 'Stat' status registers for the 50g/100g/200g and 400g rates when using the Ethernet Subsystem FPGA IP?
Description Due to a problem in the Ethernet Subsystem FPGA IP version 23.3, the user will be unable to access any status registers using AXI-Lite. Resolution There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Ethernet Subsystem FPGA IP.Why are packet counters rolling over within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, the packet counters within the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP will roll over when small back-to-back packets are encountered, and the packet counters are nearing the saturated value (i.e., all F’s). Resolution There is no workaround for this problem. This problem has been fixed in version 23.2 of the Intel® Quartus® Prime Pro Edition Software.Why is the eCPRI FPGA IP unable to run on hardware using Stratix® 10 E-Tile with the Nios® V Processor for FPGA and turn on the interworking function (IWF)?
Description Due to a problem in the eCPRI FPGA IP version 3.0.2 in the example design, you may find that there is an error shown at the 10G transaction after changing the dynamic reconfiguration process from 25G to 10G. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the CPRI Intel® FPGA IP Design Example for 24G variants with the Intel® Stratix® 10 L/H-Tile device fail to simulate when using the Cadence Xcelium* simulator?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, you might see the CPRI Intel® FPGA IP Design Example for 24G variants with the Intel® Stratix® 10 L/H-Tile device fails to simulate when using the Cadence Xcelium* simulator. Resolution There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Why is the Fronthaul Compression FPGA IP Example Design unable to meet timing requirements, especially with the Stratix® 10 FPGA H-Tile?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, you may see a timing failure when the Data Direction is set to "TX and RX" and the Compression Method is set to "BFP". Resolution This problem is fixed in 24.2 release of the Quartus® Prime Pro Edition Software.Why does the Quartus® Prime Pro, Support Logic Generation stage fail in a design with multiple instances of the F-Tile Ethernet Multirate FPGA IP when the option Enable dedicated CDR clock output has been selected?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the Support Logic Generation stage of compilation will fail in a design with multiple instances of the F-Tile Ethernet Multirate FPGA IP if the variants have enabled the Enable dedicated CDR clock output option. Resolution There is no workaround for this problem. This problem has been fixed in version 23.4 of the Quartus® Prime Pro Edition Software.Why does the Interlaken (2nd Generation) Intel® FPGA IP fail to generate an evaluation mode programming file?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1, the Interlaken (2nd Generation) Intel® FPGA IP doesn't support the Intel® FPGA IP Evaluation Mode for time-limited programming file (.sof) generation. Resolution To work around this problem, follow the steps below: Download a copy of uflex_ilk_tx_ext.ocp and uflex_ilk_rx_regroup_n.ocp files Place a copy of uflex_ilk_tx_ext.ocp under <IP_generation_folder>/altera_uflex_ilk_<xxxx>/synth/uflex_ilk_mac/ Place a copy of uflex_ilk_rx_regroup_n.ocp under <IP_generation_folder>/altera_uflex_ilk_<xxxx>/synth/uflex_ilk_regroup/ Add the lines below to the Intel® Quartus® Prime IP File of your IP variant <IP_generation_folder>/<IP_name>.qip Recompile your design set_global_assignment -library "altera_uflex_ilk_<xxxx>" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_uflex_ilk_<xxxx>/synth/uflex_ilk_mac/uflex_ilk_tx_ext.ocp"] set_global_assignment -library "altera_uflex_ilk_<xxxx>" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_uflex_ilk_<xxxx>/synth/uflex_ilk_regroup/uflex_ilk_rx_regroup_n.ocp"] * Remember to substitute <xxxx> with the four-digit number that was assigned to your IP variant after IP generation This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software 21.2.Why am I seeing error for GTS CPRI PHY FPGA IP Example Design with Development kit option enabled for 24G or 12G rates in the Quartus® Prime Pro Edition Software version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the GTS CPRI PHY FPGA IP GUI allows users to generate a Development kit-based Example Design with 24G and 12G rates, even though the Agilex™ 5 E-Series Development kit does not support 24G and 12G data rates. The GUI should block these configurations, but it does not in the Quartus® Prime Pro Edition Software version 24.3. Resolution To avoid this error, please select only 10G or below rate while generating the GTS CPRI PHY FPGA IP Example Design with Development kit option selected. This problem is fixed in 24.3.1 release of the Quartus® Prime Pro edition software.