Why is the o_rx_pfc port enabled for longer durations than normal when generating designs at 400G SIP using the F-Tile Ethernet Hard IP with Priority Flow Control (PFC) enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see longer durations of “o_rx_pfc” port enabled in the example designs generated using the F-Tile Ethernet Hard IP at data rates of 400G SIP with PFC enabled. When PFC is enabled, if packets received are more than the maximum configured frame size of the receiver, along with which if packet truncation is also enabled on the receiver side, then the packets are truncated, causing data_valid to deassert. This deasserted data_valid signal is affecting the counters of o_rx_pfc to stretch the pause signal duration. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the AXI-Lite interface read 'x' in simulation when attempting to access the 'Stat' status registers for the 50g/100g/200g and 400g rates when using the Ethernet Subsystem FPGA IP?
Description Due to a problem in the Ethernet Subsystem FPGA IP version 23.3, the user will be unable to access any status registers using AXI-Lite. Resolution There is no workaround for this problem. This problem is scheduled to be fixed in a future release of the Ethernet Subsystem FPGA IP.Why does the HDMI 2.1 Intel® FPGA Source IP output the wrong VSYNC and HSYNC polarity?
Description Due to a problem starting from the Intel® Quartus® Prime Pro Edition Software version 19.4, you may see the HDMI 2.1 Intel® FPGA Source IP in TMDS mode output incorrect VSYNC and HSYNC polarity. This problem only impacts the HDMI 2.1 Intel® FPGA Source IP in TMDS mode. This problem does not impact HDMI 2.1 Intel® FPGA Source IP in FRL mode or HDMI 2.0 Intel® FPGA Source IP Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.Why are TLPs being lost when using the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.2, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express may fail to capture the pX_tx_st_eop_i signal assertion from the application logic at the Avalon® Streaming TX interface. As a result, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express will drop the Avalon® Streaming packet and will not generate the corresponding Transaction Layer Packet (TLP). The following Avalon® Streaming packet delivered to the Avalon® Streaming TX interface may not be affected by this problem. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3.Why do I see the problem "Internal loopback button" grey out after enabling it when using internal loopback in the Quartus® Prime Pro Edition Software version 21.3?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 21.3, you will see the problem "Internal loopback button" grey out when using internal loopback in the system console. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 22.4.Why does the O-RAN Intel® FPGA IP give incorrect values when the Mu-law compression is turned on?
Description Due to a problem in the O-RAN Intel® FPGA IP version 1.8.0 and earlier, you may see the O-RAN Intel FPGA IP gives incorrect values when the Mu-law compression is turned on. When the compressed IqWidth and the original PRB value combination match as per below, the O-RAN Intel FPGA IP may generate an incorrect value of compressed PRB. IqWidth 8: Original PRB Value 0xFFC0 IqWidth 9: Original PRB Value 0xFFE0 IqWidth 10: Original PRB Value 0xFFF0 IqWidth 11: Original PRB Value 0xFFF8 IqWidth 12: Original PRB Value 0xFFFC IqWidth 13: Original PRB Value 0xFFFE IqWidth 14: Original PRB Value 0xFFFF For example, the original PRB value "0xFFF8" is compressed to 11 bits with comp Shift value '0' and the compressed PRB value is incorrectly generated as 0 (0x0). The correct compressed PRB value should be -1 (0x7FF). The Fronthaul Compression Intel® FPGA IP has the same problem. Resolution This problem is scheduled to be fixed in the O-RAN Intel® FPGA IP Version 1.8.1 and the Fronthaul Compression Intel FPGA IP 1.0.4.Error: SDC_ENTITY not allowed for EFileKind, must be in {[VERILOG, VERILOG_ENCRYPT, SYSTEM_VERILOG, SYSTEM_VERILOG_ENCRYPT, VERILOG_INCLUDE, SYSTEM_VERILOG_INCLUDE, VHDL, VHDL_ENCRYPT, SDC, MIF, HEX, DAT, QXP, HPS_ISW, PLI_LIBRARY, VPI_LIBRARY, OTHER]}
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 21.1, the error message above may be seen while executing 'generate HDL' for the Error Message Register Unloader Intel® FPGA IP Core when using Intel® Stratix® V, Intel® Arria® V, or Intel® Cyclone® V devices. The full error message is shown below: Error: SDC_ENTITY not allowed for EFileKind, must be in {[VERILOG, VERILOG_ENCRYPT, SYSTEM_VERILOG, SYSTEM_VERILOG_ENCRYPT, VERILOG_INCLUDE, SYSTEM_VERILOG_INCLUDE, VHDL, VHDL_ENCRYPT, SDC, MIF, HEX, DAT, QXP, HPS_ISW, PLI_LIBRARY, VPI_LIBRARY, FLI_LIBRARY, OTHER]} while executing "add_fileset_file $sdc_file SDC_ENTITY PATH $sdc_file {NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION}" (procedure "generate_verilog_fileset" line 24) invoked from within "generate_verilog_fileset $name $ifdef_params_list" (procedure "generate_synth" line 9) invoked from within "generate_synth altera_emr_unloader" Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition Software version 21.1 Download and install Patch 0.08std for the Intel® Quartus® Prime Standard Edition Software version 21.1 from the appropriate link below: (To download the .run file, right-click on the above link and choose “Save link as”) Intel® Quartus® Prime Standard Edition Software version 21.1 patch: Download patch 0.08std for Windows (.exe) Download patch 0.08std for Linux (.run) Download the Readme for patch 0.08std (.txt) This problem is fixed starting from Intel® Quartus® Prime Standard Edition Software version 22.1.Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the error below will be seen when using Questasim* Intel® FPGA Edition to simulate a design that instantiates the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express*. Error: ../../../../pcie_ed_rp/ip/pcie_top/pcie/intel_rtile_pcie_ast_300/sim/pcie_intel_rtile_pcie_ast_300_mqi6v2a.sv(63124): Module 'rtile_s20_v0' is not defined Resolution To work around this problem, use the Siemens* Questa* Advanced Simulator full version. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition Software.Why am I unable to detect a user MSI-X from the Multi Channel DMA Intel® FPGA IP for PCI Express in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, the user MSI-X feature in the Multi Channel DMA Intel® FPGA IP for PCI Express is not functional. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3.Why is the F-Tile Ethernet FPGA Hard IP with flow control enabled getting blocked from sending traffic when it receives PFC frames from a link partner?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and earlier, the F-Tile Ethernet FPGA Hard IP with flow control enabled is blocked from sending traffic when it receives PFC (Priority-based Flow Control) frames from the link partner. Traffic is usually blocked when the parameter Stop TX traffic when the link partner sends pause in the IP GUI is set to Yes. Here, you can see o_tx_ready going low, leading to traffic blocking. Resolution This problem is fixed beginning with the Quartus Prime Pro Edition software version 24.1.