Why does the O-RAN Intel® FPGA IP give incorrect values when the Mu-law compression is turned on?

Description

Due to a problem in the O-RAN Intel® FPGA IP version 1.8.0 and earlier, you may see the O-RAN Intel FPGA IP gives incorrect values when the Mu-law compression is turned on.

When the compressed IqWidth and the original PRB value combination match as per below, the O-RAN Intel FPGA IP may generate an incorrect value of compressed PRB.

IqWidth 8: Original PRB Value 0xFFC0
IqWidth 9: Original PRB Value 0xFFE0
IqWidth 10: Original PRB Value 0xFFF0
IqWidth 11: Original PRB Value 0xFFF8
IqWidth 12: Original PRB Value 0xFFFC
IqWidth 13: Original PRB Value 0xFFFE
IqWidth 14: Original PRB Value 0xFFFF

For example, the original PRB value "0xFFF8" is compressed to 11 bits with comp Shift value '0' and the compressed PRB value is incorrectly generated as 0 (0x0). The correct compressed PRB value should be -1 (0x7FF).

The Fronthaul Compression Intel® FPGA IP has the same problem.

Resolution

This problem is scheduled to be fixed in the O-RAN Intel® FPGA IP Version 1.8.1 and the Fronthaul Compression Intel FPGA IP 1.0.4.