Why does the HDMI 2.1 Intel® FPGA Source IP output the wrong VSYNC and HSYNC polarity?

Description

Due to a problem starting from the Intel® Quartus® Prime Pro Edition Software version 19.4,  you may see the HDMI 2.1 Intel® FPGA Source IP in TMDS mode output incorrect VSYNC and HSYNC polarity. 

• This problem only impacts the HDMI 2.1 Intel® FPGA Source IP in TMDS mode.

• This problem does not impact HDMI 2.1 Intel® FPGA Source IP in FRL mode or HDMI 2.0 Intel® FPGA Source IP

Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. 

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.