Why does the AXI-Lite interface read 'x' in simulation when attempting to access the 'Stat' status registers for the 50g/100g/200g and 400g rates when using the Ethernet Subsystem FPGA IP?

Description

Due to a problem in the Ethernet Subsystem FPGA IP version 23.3, the user will be unable to access any status registers using AXI-Lite.

Resolution

There is no workaround for this problem.
This problem is scheduled to be fixed in a future release of the Ethernet Subsystem FPGA IP.