Agilex 7 dk_si_agi027fa FPGA issue
Hello. My name is Moti. I am working on a project with agilex 7 that requires me to create a driver to communicate with the FPGA registers of agilex 7 dk_si_agi027fa. The first step was to build GSRD for this board. We followed the instructions in this page: https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/#build-flow We flashed the results (u-boot, fs and linux images) to an sd card, and I was able to bring up linux on the board with a sample driver (that works properly). Unfortunately, I wasn't able to communicate with any fpga registers. The following output: root@MiWiFi-RA80-srv:~# cat /sys/class/fpga_manager/fpga0/state unknown leads us to understand that the .rbf file wasn't loaded properly, and needs to be loaded into the board. (state "unknown" means fpga is not configured -> probably because the .rbf file wasn't loaded). we want to ask: - Is that the correct next step? - I am using agilex7_dk_si_agi027fa_gsrd_ghrd.core.rbf as mentioned in GSRD - is that the correct one? - how do I load the .rbf? i tried following instructions from the web - copied it to the sd card and ran the following command, but I keep receiving "error 4": SOCFPGA_AGILEX # fatload mmc 0:1 0x2000000 agilex7_dk_si_agi027fa_gsrd_ghrd.core.rbf 1658880 bytes read in 77 ms (20.5 MiB/s) SOCFPGA_AGILEX # fpga load 0 0x2000000 ${filesize} .. U-Boot SMC: Error sending bitstream! SDM: Config status: (0xf0040000) SDM Err: Bitstream element not understood. Internal error. Catchall Error. Command 'load' failed: Error 4 I also noticed fpga fails to load during boot and the errors seem similar to the ones i get when i try to manually load the .rbf file: ## Loading fpga from FIT Image at 02000000 ... Trying 'fpga-4' fpga subimage Description: FPGA bitstream for GHRD Type: FPGA Image Compression: uncompressed Data Start: 0x0297e764 Data Size: 1658880 Bytes = 1.6 MiB Load Address: 0x0a000000 Hash algo: crc32 Hash value: 654d6710 Verifying Hash Integrity ... crc32+ OK Loading fpga from 0x0297e764 to 0x0a000000 .. U-Boot SMC: Error sending bitstream! SDM: Config status: (0xf0040000) SDM Err: Bitstream element not understood. Internal error. Catchall Error. .. U-Boot SMC: Error sending bitstream! SDM: Config status: (0xf0040000) SDM Err: Bitstream element not understood. Internal error. Catchall Error. FPGA image is corrupted or invalid Your assistance on the above will be much appreciated. Thanks.
Adding ARM core in Agilex5 Eagle board project
Hello, I added the Nios processor in my project using Agilex HPS. I want to learn how to add ARM cores to the system. I am not planning on adding any OS , but will use barebone C code generated from Simulink. Please point to any training material for adding ARM core to the FPGA. Thanks. Nangavalli.
"DMA engine initialization failed" error when EMAC uses GMII interface
I am seeing the error given here when I boot the Agilex A5 (Quartus 24.3). This doc recommends to connect mac_tx_clk_i to a 2.5/25 MHz clock source 'correctly'. What does it mean, 'correctly'? There is a field in the HPS docs for this signal here, but this also does not specify what 'correctly' means. For further reference, I am trying to connect EMAC0 to EMAC1. Also here is the .dts: &gmac0 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; fixed-link { speed = <1000>; full-duplex; }; }; &gmac1 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; fixed-link { speed = <1000>; full-duplex; }; }; Many thanks! K
DE2-35 send .hex image to PC through USB port
Hi guys! I'm doing an image processing project using the DE2-35 kit. So I have the image file in ".hex" format and I my workflow is: Load the ".hex" image (300KB) into the SRAM of the DE2-35 kit (512KB), and the MCU will access the SRAM to process the image (grayscale to be specific). After finishing processing the image, it will move the processed image to the USB port to transfer the image to my PC for display. I've successfully loaded the ".hex" image to the SRAM (It's a pain because there is only 512KB of SRAM) My questions are: 1. How do I process the image? 2. How do I move the processed image to the USB port for data transfer? 3. Is there a better way to transfer the processed image to my PC and how can I do it?EPCS64 access from HPS on Cyclone V
Hi, I am working on Terasic SoC System on Module Evaluation KIT. I am trying to configure FPGA from HPS through FPPx32 configuration scheme and then read/copy EPCS64 sector to HPS DDR3 memory. MSEL is configured to 01010 using on board DIP switch. I can see that FPGA portion is configured successfully but data read from EPCS64 are all 0xFF. Please note that EPCS64 sector is programmed and verified with non 0xFF data. Serial Flash Controller IP slave memory interface is connected to master interface of Avalon-MM Pipeline bridge and slave interface of Avalon-MM Pipeline bridge is connected to h2f_axi_master interface of hps_0 in platform designer. Can MSEL in HPS scheme makes EPCS64 invisible to HPS ? Is there any application note or design example to access EPCS from HPS when FPGA is configured in FPPx32 mode ? Best Regards, Naresh
5CSXFC2C6U23C8N_pinout
For PN"5CSXFC2C6U23C8N" Pin named"HPS_TRST" have a description as an active low pin, however, name doesn't have any letter indicated that like"HPS_nRST", which have letter n for that. can please confirm " is this pin"HPS_TRST" is active low and what letter should added in symbol for indicate that ?
Linux UIO IRQ related periodic CPU usage
Hi, I have an Intel Arria 10 SoC FPGA system with 5.4.104-lts Linux built with Yocto 3.3.1 and Poky. The installed FPGA image is doing nothing more than making interrupts to an UIO device, 50 times a sec. The UIO device is defined in the device tree like this: tx_trig_irq { /* /dev/uio4 */ compatible = "test_irq", "generic-uio"; interrupts = < 0 0x16 IRQ_TYPE_EDGE_RISING >; interrupt-parent = <&intc>; }; The interrupts arrive in the OS correctly. Here is the simple program which handles the interrupts, there is no other software running. #include <iostream> #include <cmath> #include <fcntl.h> #include <unistd.h> typedef struct { int txTrigIrqFd; } TX_IRQ_HANDLE_S; bool wait_for_irq (TX_IRQ_HANDLE_S* pHandle) { if (!pHandle || pHandle->txTrigIrqFd < 0) { std::cout << "ERROR: handle"; return false; } uint32_t info = 1; ssize_t nb = write(pHandle->txTrigIrqFd, &info, sizeof(info)); if (nb != (ssize_t)sizeof(info)) { std::cout << "ERROR: writing"; return false; } nb = read(pHandle->txTrigIrqFd, &info, sizeof(info)); if (nb == (ssize_t)sizeof(info)) { return true; } return false; } int main(int argc, char* argv[]) { //Init IRQ TX_IRQ_HANDLE_S* tx_irq_handle = NULL; tx_irq_handle = (TX_IRQ_HANDLE_S*) ( malloc (sizeof (TX_IRQ_HANDLE_S)) ); if (!tx_irq_handle) { std::cout << "irq init failed"; return 1; } tx_irq_handle->txTrigIrqFd = open ("/dev/uio4", (O_RDWR)); if (tx_irq_handle->txTrigIrqFd < 0) { free (tx_irq_handle); std::cout << "irq init failed"; return 1; } if (!tx_irq_handle) { std::cout << "irq init failed"; return 1; } // Do IRQ while (true) { auto status = wait_for_irq(tx_irq_handle); } std::cout << "Stopped.\n"; return 0; } It handles the interrupts correctly, I also instrumented the code and see the interrupt handling's timing with Tracy, everything works as intended. However there is a strange CPU anomaly when starting this simple irq handling program: There are ~5 sec long spikes in CPU usage every minute, periodically When I reduce the number of interrupts coming from the FPGA to 25, the 1 minute period doubles to 2 minutes. When stopping the FPGA to send interrupts, and waiting some time (for eg. 1 minute), then resuming again, the priodicity of the spikes continues from the last state when the FPGA generated interrupts. So when pausing the interrupts in the midde of a spike for some minutes (the cpu usage goes to ~0%), after the resume, the CPU usage continues from the middle of the spike. The characteristics of the CPU usage graph can be tuned by doing work between the waiting for the interrupts, so the spikes can transform into a wave: // Do IRQ while (true) { //Doing some work volatile double x = 0.0001; for (int i = 0; i < 20000; ++i) { x += std::sin(x) * std::cos(x); } auto status = wait_for_irq(tx_irq_handle); } Here are some pictures: Doing no additional work: Doing some work: Doing little work Doing more work: Doing more work I've already instrumented the UIO kernel driver and watched with dmesg how the interrupt handling goes in the kernel, but I found nothing suspicious. This extra, periodical CPU usage is not assigned to any process (watching with top or htop), the cpu usage of my test program is constant, however the total cpu usage shows this periodicity. I can't imagine what is happening, I ran out of ideas. Do you have any suggestions what could cause this periodic cpu usage? Thank you!DK-SOC-1SSX-H-D
Hello I'm working with a customer who purchased part number DK-SOC-1SSX-H-D. He is needing assistance enabling the 16GB memory. Customer stated the following. "I am a developer in blackhorse solutions, working with a stratix 10 h-tile devkit, on a critical Path for a defense program. Our government program manager has assured us of our entitlement For tech support. I need some support for enabling the 16GB external memory on the devkit. I have used the supplied emif parameters for this board, which has a P-3200 rated Udimm. The parameters in the provided h-time board are for speed grade -2666, which Do not work. I have tried the speed grade -2400 with not change. The emif controller reports Calibration failed. I assume that both these settings should work for the installed micron. memory chip rated for I tried to create a ticket on intel support https://supporttickets.intel.com, with no luck as it does not Allow creation of ticket if product box is not listed in the choices offered! Please let me know if there is a more robust method for getting support for the purchased hardware/software, As we are in a critical path." Please advise.
