EPCS64 access from HPS on Cyclone V
Hi,
I am working on Terasic SoC System on Module Evaluation KIT.
I am trying to configure FPGA from HPS through FPPx32 configuration scheme and then read/copy EPCS64 sector to HPS DDR3 memory.
MSEL is configured to 01010 using on board DIP switch.
I can see that FPGA portion is configured successfully but data read from EPCS64 are all 0xFF.
Please note that EPCS64 sector is programmed and verified with non 0xFF data.
Serial Flash Controller IP slave memory interface is connected to master interface of Avalon-MM Pipeline bridge and slave interface of Avalon-MM Pipeline bridge is connected to h2f_axi_master interface of hps_0 in platform designer.
Can MSEL in HPS scheme makes EPCS64 invisible to HPS ?
Is there any application note or design example to access EPCS from HPS when FPGA is configured in FPPx32 mode ?
Best Regards,
Naresh