Request for SmartVID PMBus Compatibility Requirements for Replacing VRM on Agilex 7
Dear Altera Support Team, We are designing a board using Agilex 7 AGMA032R47A1E2VC and currently plan to use Infineon XDPE19284C as the SmartVID voltage regulator. Due to cost and design complexity considerations, we are evaluating replacing the XDPE19284C with a TI solution, such as TPS546E25 (multi-device stack configuration). Our goal is to make the VRM replacement transparent to the Agilex SDM SmartVID function. In other words, after replacement, the Agilex device should operate normally without any changes in the SmartVID behavior. We understand that SmartVID communicates with the external VRM through PMBus, and that Agilex SDM does not depend on the internal VRM implementation (such as phase number). However, we would like to confirm all the required compatibility conditions. Could you please provide a complete checklist of the PMBus parameters and behaviors that must be identical between the original VRM and the replacement VRM? For example, we would like to confirm whether the following items are required to match: 1.PMBus slave address 2.VOUT_MODE (PMBus command 0x20) 3.Linear format exponent (N value) 4.VOUT_COMMAND format and scaling 5.READ_VOUT response format 6.OPERATION command behavior 7.STATUS_WORD / STATUS_BYTE behavior 8.PAGE command support and configuration 9.PMBus bus speed requirement 10.Any required Manufacturer Specific Commands (MFR_xxxx) 11.Any other SDM-specific PMBus transactions used during SmartVID initialization In particular, we would like to know: Does Agilex SDM SmartVID use only standard PMBus commands (such as VOUT_COMMAND, READ_VOUT, STATUS_WORD, OPERATION)? Does Agilex SDM access any VRM-specific Manufacturer Commands? Does Agilex identify or depend on the specific VRM model selected in Quartus? If the Quartus setting is configured as "Other" VRM, what exact requirements must the replacement regulator satisfy? Our understanding is that the most critical parameters for a Linear PMBus regulator are: PMBus address VOUT_MODE Linear format Linear exponent N VOUT_COMMAND interpretation However, we would like to confirm this with Altera before committing to a new PCB design. Could you please provide a detailed compatibility checklist or any internal guideline/documentation regarding SmartVID VRM replacement? Thank you very much for your support. Best regards,72Views0likes0CommentsIs it possible to attach PCIe to a Dev kit?
Hello Altera Community I have the DE25 Nano dev kit from Terasic. The Altera Agilex 5 product breif says the this FPGA has PCIe, but on the Dev kit this have not been installed. The pins for this should be exposed right? Is it possible that I could attach a PCIe component myself and how would that be possible? Thanks in advance.6Views0likes1CommentAXC3000 Agilex 3 board
Hi, for a new design I'm starting to use an evaluation board from Arrow Electronics, (but designed by trenz electronics) with Agilex 3 https://github.com/ArrowElectronics/Agilex-3/wiki/Agilex-3-AXC3000-Development-Platform This board has an Hyperam W957D8NBRA4I installed but the Nios V example design uses only internal RAM. Anyone knows if the IP to use this ram is free into quartus or is necessary to acquire a license? Thanks168Views0likes6CommentsArrow AXE5 Eagle Board JTAG issue
Hi, I have an AXE5 eagle board. The Quartus Programmer on Auto-Detect does show the usb blaster3 but the device is named UNKNOWN_364F0DD instead of A5ED065BB32AES4. What do you think could be the issue? BTW I am on Linux RHEL 8. I am using Arrow blaster and used FTProg to flash it as USB Blaster 3 as suggested by guide83Views0likes2CommentsPDN file and PCB decoupling
Hello, In the PDN excel file how is determined the ESR and ESL value for the decoupling capacitor ? I would like to add bigger capacitor . Is there some explanation for this file ? all the cells are locked. Is there some explanation to help to determine the number of capacitor needed for an application. I put the power rail voltage and current and now I need to determine the capacitor decoupling for each rail. I'm using a 5CEFA4_M13 chip on my board. Thanks for your help49Views0likes1CommentEPM9320LI84-20
Hello! Could you please clarify something? Within the same batch of EPM9320LI84-20 FPGAs, the marking quality varies significantly, which is especially noticeable in the letter A in the ALTERA logo. This is not an isolated case within the batch—there are several chips with the same issue. Could this happen during manufacturing? As you understand, these chips were discontinued long ago and are no longer available from official distributors, so we have to source them from less reliable suppliers. Please respond as soon as possible. Thank you!107Views0likes4CommentsTerasic Atum A3 Nano
Hi, I am working through the getting started manual for this board which is generally pretty good. However there are no examples of how to use the SDRAM or the Ethernet PHY on this board. It is not clear to me if there is any IP that can be added for the SDRAM or the ethernet. Are there any examples of how to use both functions? I bought the board assuming that these functions were included and I could just add my own custom IP application. Do I have to write my own VHDL for these functions and then the low level C drivers or are there examples? Any help would be much appreciated. Thanks169Views0likes9Comments