Showing results for lpddr2Search instead for LPDDR488 ResultsMost relevantDoes the ALTDQ_DQS2 IP support LPDDR2 memory?Description The ALTDQ_DQS2 IP does not support LPDDR2 memory. LPDDR2 memory requires the DQS Tracking feature to align the DQS, and DQS Enable signals. The ALTDQ_DQS2 IP does not s...SoC HPS Interface to LPDDR2 is UnsupportedDescription LPDDR2 memory is unsupported for the Arria V SoC and Cyclone V SoC in certain releases of the Quartus II software. Resolution Update the Quartus II software to v13.1dp1 or later, and r...Why are there data errors on the HPS LPDDR2 interface?Description Due to a problem in the SoC EDS software version 16.0 and earlier, data errors may be seen on Cyclone® V SoC and Arria® V SoC HPS SDRAM interfaces in LPDDR2 mode. Hard or soft LPDDR2...LPDDR2 GUI Mismatch for Mode Register 2Description This problem affects LPDDR2 products. The user interface incorrectly indicates an available Mode Register 2 (MR2) setting of CAS Latency. In reality, the interface should show the a...LPDDR2 Timing Closure Problem with Arria V DevicesDescription This problem affects LPDDR2 products. LPDDR2 interfaces targeting Arria V devices may not close timing. Resolution This issue will be fixed in a future version. There is no w...Default tCCD for LPDDR2 Devices Hard Codes to 2 CyclesDescription This problem affects LPDDR2 products. This issue applies to LPDDR2 interfaces, when an LPDDR2-S2 memory device is used. Generated example designs always set tCCD=2 cycles for LPDDR2 d...DQS# Enable Option Must be Enabled for LPDDR2 InterfacesDescription This problem affects LPDDR2 products. The LPDDR2 interface supports only differential DQS signals. The DQS# Enable option on the Memory Parameters tab in the parameter editor must be e...Deep Power Down Issue With LPDDR2 Interfaces on Cyclone V DevicesDescription This problem affects LPDDR2 products. In LPDDR2 interfaces targeting Cyclone V devices, if the auto power down mode is enabled, the HPC II memory controller cannot immediately issue a...Timing Closure for Soft LPDDR2 Interfaces May Not be RobustDescription This problem affects LPDDR2 products. Soft LPDDR2 interfaces targeting Arria V or Cyclone V devices may have difficulty achieving timing closure. Resolution The workaround for this i...Possible to Select Unsupported Device Family for LPDDR2 InterfaceDescription This problem affects LPDDR2 memory interfaces. Altera LPDDR2 memory interfaces support only Arria V and Cyclone V device families; however, it is possible in Qsys to select other, u...