Why is the bus ordering reversed in the Technology Map Viewer?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see that the bus ordering is reversed in the Technology Map Viewer. This problem occurs when a design contains a Block Design File (BDF) whose output bus is connected to a SystemVerilog HDL packed array from a top-level SystemVerilog HDL module.

For example, the expected mapping in the Technology Map Viewer is:

• inst0 -> Out[0]
• inst1 -> Out[1]
• inst2 -> Out[2]
• inst3 -> Out[3]

However, the actual mapping after compilation in the Technology Map Viewer become:

• inst0 -> Out[3]
• inst1 -> Out[2]
• inst2 -> Out[1]
• inst3 -> Out[0]

Resolution

To work around this problem, do one of the following:

• Convert the BDF file to Verilog HDL or VHDL.

• • Open the BDF file in the Quartus® Prime Standard Edition Software.
  • Select File > Create / Update > Create HDL Design File from Current File.
  • Choose Verilog HDL or VHDL.
  • Replace the original BDF module in the Quartus® Prime Pro Edition Software project with the generated HDL file.

• Explicitly reorder the bits in the top-level SystemVerilog HDL module by using a SystemVerilog HDL streaming operator in the port connection.