Why do I see a large timing violation when using the IOPLL IP’s Non-Dedicated Feedback Path option?

Description

A timing violation may occur when the Non-Dedicated Feedback Path option is enabled in the IOPLL IP. This is caused by the C-counter starting to toggle unexpectedly, resulting in a phase shift of the output clocks relative to the input clock.

This problem affects the following device families:

• Stratix® 10 FPGAs
• Agilex™ 3 FPGAs
• Agilex™ 5 FPGAs
• Agilex™ 7 FPGAs

Resolution

To address this timing violation, add multi-cycle constraints to the impacted timing paths.

1) The set_multicycle_path constraint should only be applied to the affected path.

2) The affected clock domain can be either the source or the destination clock domain in the timing transfers that this behavior may impact.