hi, everyone. I have read code from the DE2 I2Sound Demonstration and compared with WM7831 datasheet. Everything is quite clear, except the setting of sample rate. According to the datasheet, when using sample rate of 48 khz, mclk frequency is required to be 12.288 mhz. http://hahoangthach.googlepages.com/sample.jpg but the demonstration provides the clock of 25 mhz ( 50/2 AUD_XCK pin). I have also check the configure of CLKIDIV2 in sampling control register, core clock is also MCLK ( not divided by 2 ). Could you please explain me why ?? Because I intend to use the sample rate of 44.1 Khz and don't know what frequency for MCLK. http://hahoangthach.googlepages.com/sample2.jpg

--- Quote Start --- But the demonstration provides the clock of 25 Mhz ( 50/2 AUD_XCK pin). --- Quote End --- It's divided by 4, not by 2. The output clock changes state every second pulse of the input clock. So the full cycle is every four incoming clock pulses. Simulate it for better understanding. Also, as you can see in the table, it doesn't have to be 12.288 MHz. It can also be 18.432 MHz. It depends on the BOSR bit. Instead of using a divided clock, you can use a PLL to get a clock closer to the nominal value.

--- Quote Start --- It's divided by 4, not by 2. The output clock changes state every second pulse of the input clock. So the full cycle is every four incoming clock pulses. Simulate it for better understanding. --- Quote End --- thank you, It is really divided by 4, I have misunderstood because of the name CLOCK_2. Therefore the MCLK is 12.5 Mhz ~ 12.288 Mhz. It is clear now. --- Quote Start --- Also, as you can see in the table, it doesn't have to be 12.288 MHz. It can also be 18.432 MHz. It depends on the BOSR bit. --- Quote End --- yes, in the demonstation, they set BOSR =0. ROM= 16'h1000; //mclk so, for the sample rate of 44.1 khz, i need to divide 50 mhz by 3 ( 16.667 mhz ~ 16.9344 mhz ) and set bosr = 1 ? --- Quote Start --- Instead of using a divided clock, you can use a PLL to get a clock closer to the nominal value. --- Quote End --- Thank you for your suggestion.

--- Quote Start --- So, for the sample rate of 44.1 Khz, I need to divide 50 Mhz by 3 ( 16.667 Mhz ~ 16.9344 Mhz ) and set BOSR = 1 ? --- Quote End --- Yes, but you can't just divide a clock by 3 without violating duty cycle restrictions. You would need to use a PLL. When using a PLL, set the wanted frequency in the PLL MegaWizard. The MegaWizard will take care of selecting the best multiplication/division.

--- Quote Start --- Yes, but you can't just divide a clock by 3 without violating duty cycle restrictions. You would need to use a PLL. When using a PLL, set the wanted frequency in the PLL MegaWizard. The MegaWizard will take care of selecting the best multiplication/division. --- Quote End --- thank you very much. I will use PLL as you suggest. >:D<

Hi guys , I'm trying to understand the audio demo example for the altera De2 that comes into the CD I'm reading the datasheet from wolfson(wm8731). At moment I doesn't know how they are using the index in the ROM array. ROM[0]= 16'h0c00; //power down ROM[1]= 16'h0ec2; //master ROM[2]= 16'h0838; //sound select ROM[3]= 16'h1000; //mclk ROM[4]= 16'h0017; // ROM[5]= 16'h0217; // ROM[6]= {8'h04,1'b0,vol[6:0]}; // ROM[7]= {8'h06,1'b0,vol[6:0]}; //sound vol //ROM[4]= 16'h1e00; //reset ROM[`rom_size]= 16'h1201;//active Can you explain me please? Thank you.

Question about sample rate of audio codec WM8731 on DE2

15 Replies

Altera_Forum
Honored Contributor
17 years ago
Hi friend, don't worry I've fixed the problem.

I run the program from the NIOS 2 IDE and works !

Thank you so much
Altera_Forum
Honored Contributor
17 years ago
hi everyone,

I'm trying to transmit audio data with wireless devices, I take a look on the DE1_i2sound project on DE1 cd, I saw that AUD_DACLRCK pin assigned to AUD_ADCDAT pin if I assign AUD_DACLRCK to input of my wireless tranciever and assign AUD_ADCDAT to my receiver will that work? or should I work on I2C controller?
Altera_Forum
Honored Contributor
17 years ago
--- Quote Start ---
hi everyone,

I'm trying to transmit audio data with wireless devices, I take a look on the DE1_i2sound project on DE1 cd, I saw that AUD_DACLRCK pin assigned to AUD_ADCDAT pin if I assign AUD_DACLRCK to input of my wireless tranciever and assign AUD_ADCDAT to my receiver will that work? or should I work on I2C controller?
--- Quote End ---

I dont know about DE1_i2sound on DE1 cd, but I think it is the same with one on DE2. In i2sound Demo, it doesnt matter what AUD_ADCDAT is assigned to, it just simply configures the WM8731 codec so that line input from mic is connected to speaker ( by pass or side tone mode - i dont remember :p ).

It is not clear about your project, whether DE1 is source or sink. If you want DE1 could play sound from other devices via wireless, make sure that devices line-out is transmitted to AUD_ADCDAT. You also need information such as sampling frequency, bits per sample to generate correctly BCLK, AUD_DACLRCK ....etc.
Altera_Forum
Honored Contributor
15 years ago
Chào anh !
Tôi vừa mới bắt đầu tìm hiểu về DE1 của Altera . Chủ đề là thiết kế một game trên DE1 . Tôi đang vướng mắc về phần audio codec của WM8731 . Không biết anh có phiền khi chỉ dẫn cho tôi về phần này không ? Như là tôi sẽ bắt đầu từ đâu và làm những cái gì ? Cảm ơn anh !
Nguyễn Văn Hiến
mrnguyenhien@gmail.com
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
It's divided by 4, not by 2. The output clock changes state every second pulse of the input clock. So the full cycle is every four incoming clock pulses. Simulate it for better understanding.

Also, as you can see in the table, it doesn't have to be 12.288 MHz. It can also be 18.432 MHz. It depends on the BOSR bit.

Instead of using a divided clock, you can use a PLL to get a clock closer to the nominal value.
--- Quote End ---

Hi,

I'm trying to configure WM8731 Codec on DE2 board as an ADC. But i have no idea how the whole thing works. I'd like to pump in music through WM8731 Codec, and pass the music signal to FPGA (I have designed a LPF and program in cyclone II), then obtain the filtered music signal through WM8731 Codec again. The purpose that using WM8731 Codec is just to demo the audio signal filtering process in real time. I'd like to disable the filtering function that provided by WM8731 Codec. Other than configuring WM8731 Codec, i will need another file for configuring i2c so that WM8731 Codec can communicate with FPGA (cyclone II) ? Am i rite? My filter is designed to have sampling frequency of 10Khz, what frequency should i use for master clock?

Please guide me through this. If possible, i'd like to have a copy of codes as reference. I'm just a beginner. Your help will be appreciated :)

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Question about sample rate of audio codec WM8731 on DE2

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