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It's divided by 4, not by 2. The output clock changes state every second pulse of the input clock. So the full cycle is every four incoming clock pulses. Simulate it for better understanding.
Also, as you can see in the table, it doesn't have to be 12.288 MHz. It can also be 18.432 MHz. It depends on the BOSR bit.
Instead of using a divided clock, you can use a PLL to get a clock closer to the nominal value.
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Hi,
I'm trying to configure WM8731 Codec on DE2 board as an ADC. But i have no idea how the whole thing works. I'd like to pump in music through WM8731 Codec, and pass the music signal to FPGA (I have designed a LPF and program in cyclone II), then obtain the filtered music signal through WM8731 Codec again. The purpose that using WM8731 Codec is just to demo the audio signal filtering process in real time. I'd like to disable the filtering function that provided by WM8731 Codec. Other than configuring WM8731 Codec, i will need another file for configuring i2c so that WM8731 Codec can communicate with FPGA (cyclone II) ? Am i rite? My filter is designed to have sampling frequency of 10Khz, what frequency should i use for master clock?
Please guide me through this. If possible, i'd like to have a copy of codes as reference. I'm just a beginner. Your help will be appreciated :)
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