Lab8: Memory Blocks problems

Hello,

I've been trying to figure out what's wrong with my design for lab8 part 2. I've implemented the RAM LPM and a hex 7segment driver but I can't seem to get it to work in my process.

Can anyone help explain?

My top-level design, where the problem exists:

Code:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.numeric_std.all;

entity part2 is

port(

KEY : in unsigned(0 downto 0);

SW : in unsigned(17 downto 0);

LEDG : out unsigned(0 downto 0);

HEX7, HEX6,

HEX5, HEX4,

HEX1, HEX0 : out unsigned(6 downto 0)

);

end part2;

architecture behavioral of part2 is

signal Qout : unsigned(7 downto 0);

signal addr : unsigned(7 downto 0);

signal wSig : unsigned(0 downto 0);

--signal clk : unsigned(0 downto 0);

signal data : unsigned(7 downto 0);

signal crap : unsigned(3 downto 0);

begin

--disregard these switches

crap(3) <= SW(16);

crap(2 downto 0) <= SW(10 downto 8);

process(KEY, SW, wSig) begin

if(KEY = "0") then

--write signal

wSig <= SW(17 downto 17);

--clock input and signification

LEDG <= "1";

if(wSig = "1") then

--memory address

addr(4 downto 0) <= SW(15 downto 11);

addr(7 downto 5) <= "000";

--data

data <= SW(7 downto 0);

end if;

end if;

end process;

mem : entity work.ramlpm port map(address => std_logic_vector(addr(4 downto 0)),

clock => KEY(0), data => std_logic_vector(data),

wren => wSig(0), unsigned(q) => Qout);

seg0 : entity work.HEX port map(Qout(3 downto 0), HEX0);

seg1 : entity work.HEX port map(Qout(7 downto 4), HEX1);

seg4 : entity work.HEX port map(data(3 downto 0), HEX4);

seg5 : entity work.HEX port map(data(7 downto 4), HEX5);

seg6 : entity work.HEX port map(addr(3 downto 0), HEX6);

seg7 : entity work.HEX port map(addr(7 downto 4), HEX7);

end behavioral;

The generated memory block LPM(I've taken the copyright info out of this file in order to fit it into one forum post. I apologize if this might cause any issues.)

See attached for the generated memory block of LPM

See attached for the 7 seg code