Lab8: Memory Blocks problems

Currently, you are not using KEY0 as a clock, you are just using it as an enable (active low). At the moment if anything changes while KEY0 is '0' then the output will change too. To be a clock, you need to change outputs on the rising/falling edge of that signal. You can do that by:

if rising_edge(KEY0) then... --or falling_edge(), but not both

If KEY0 is not a real clock, but a signal generated elsewhere, you could run into problems with setup and hold times. You need a globally distributed signal to act as a proper clock (which is usually an actually clock).

With LEGD, you set it to '1', but you never set it back to '0'. So the first time KEY0 is '0', LEGD gets latched to '1' and never changes.