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Altera_Forum
Honored Contributor
15 years agoLab8: Memory Blocks problems
Hello, I've been trying to figure out what's wrong with my design for lab8 part 2. I've implemented the RAM LPM and a hex 7segment driver but I can't seem to get it to work in my process. Can anyon...
Altera_Forum
Honored Contributor
15 years agoyou've declared key as an unsigned which is an array. std_logic is not, so you can't type convert. because unsigned is just an array of std_logic, you just need to index a single element.
if rising_edge(key(0)) then ...