Lab8: Memory Blocks problems

Hello,

Work and life have kept me from my hobby, even though it's been scratching at the back of my mind all this time. So now i finally have a chance to look at this stuff again and I'm having trouble with type conversion.

Taking your advice, Tricky, I've changed my if to:

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if(rising_edge(KEY)) then

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But this gives me the error:

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Error (10476): VHDL error at part2.vhd(35): type of identifier "KEY" does not agree with its usage as "std_ulogic" type

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So then i try to change this to:

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if(rising_edge(std_logic(KEY))) then

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But I get an error saying:

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Error (10305): VHDL Type Conversion error at part2.vhd(35): cannot convert type "UNSIGNED" to type "std_logic"

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I've googled VHDL type conversion for over an hour now and can't seem to find an answer. For all its type safety, VHDL design practice documentation seems to lack very much. Could someone please help?