I'm trying to implement a PI controller in FPGA using schematic entry method in altera quartus II . I'm using the following equivalent PI controller equation, c(n) = c(n-1)+kp*(e(n)-e(n-1))+Ki*T*e(n-1) where, c(n) = controller output Kp= proportional constant Ki=integral constant e(n)=Reference -actual input T=sampling period I'm implementing it for 8 bit data. I couldnot implement c(n-1) in the above equation using schematic entry. Can someone help me implement this? I would be grateful if you can suggest me other ways of implementing PI controller like in VHDL.

Looks like you will need a storage element. Perhaps a fifo would work or a D-flipflop with an enable.

gmpstr, Thanks a lot for response. I used D type flip flop and I sucessfully implemented kp*(e(n)-e(n-1))+Ki*T*e(n-1) but once I took the c(n) and pass it through D type flip flop to get c(n-1) and add to above, my problem started. The value of c(n-1) is always zero though it acutally is not and the result is just always equal to kp*(e(n)-e(n-1))+Ki*T*e(n-1). During synthesis, I got the following warning, Warning (14130): Reduced register "lpm_dff0:inst9|lpm_ff:lpm_ff_component|dffs[0]" with stuck data_in port to stuck value GND Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "output[0]" is stuck at GND Maybe this will help you understand my problem. I hope to get feedback from you in this matter.

You need to figure out why the data_in port is being reported as stuck at GND. You could post a quartus archive of the design and I'm sure you would get feedback that would solve the issue.

--- Quote Start --- I'm trying to implement a PI controller in FPGA using schematic entry method in altera quartus II . I'm using the following equivalent PI controller equation, c(n) = c(n-1)+kp*(e(n)-e(n-1))+Ki*T*e(n-1) where, c(n) = controller output Kp= proportional constant Ki=integral constant e(n)=Reference -actual input T=sampling period I'm implementing it for 8 bit data. I couldnot implement c(n-1) in the above equation using schematic entry. Can someone help me implement this? I would be grateful if you can suggest me other ways of implementing PI controller like in VHDL. --- Quote End --- Hi, can you post your schematic ? If you don't what to use VHDL , maybe Verilog could be a choice ? Kind regards GPK

Some years ago, I started programming DSP applications with maxplus2 and schematic entry.You can achieve any kind of arithmetic utilizing the respective MegaFunctions. However, you have to assure, that c(n) sum doesn't overflow. Standard add and sub operators or megafunctions don't provide saturation logic, you have to add it separately.

Implementation of Digital PID controller in FPGA

30 Replies

Altera_Forum
Honored Contributor
14 years ago
Mr. Frank,
you are right, and i don't want a supervisor for my research because i already have one:). i just didn't see any comment since August,2010.

now i'm working to understand the control and design part of digital PID , and the next step after finishing the simulation of the PID is to implement it based of FPGA.

I have only one question, i'm going to buy Altera DE2-70 , according to your experince in this field do you think it's sufficient to implement the PID.

Please advice me which board is the good for my research:unsure: .

thanks in advanced
Altera_Forum
Honored Contributor
14 years ago
I tried to attache the board link of Altera DE2-70 but it's not allowed yet for me :(
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
I tried to attache the board link of Altera DE2-70 but it's not allowed yet for me :(
--- Quote End ---

You'll need to clarify what you mean by "board link".

The board has an Embedded USB-Blaster circuit on one of the USB connectors (it should be written on the PCB silkscreen next to the connector). I think its the outer-most connector (nearest the edge of the board).

The other two USB connectors are connected to a USB PHY for custom applications.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
You'll need to clarify what you mean by "board link".

The board has an Embedded USB-Blaster circuit on one of the USB connectors (it should be written on the PCB silkscreen next to the connector). I think its the outer-most connector (nearest the edge of the board).

The other two USB connectors are connected to a USB PHY for custom applications.

Cheers,
Dave
--- Quote End ---

The board link is the website link, sorry for confusing you :)
"To be able to post links or images your post count must be 4 or greater. You currently have 3 posts.

Please remove links from your message, then you will be able to submit your post."
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
The board link is the website link, sorry for confusing you :)

--- Quote End ---
Ah, I see.

The DE2-70 has plenty of logic for a PID controller. The lower-cost DE0-nano, BeMicro, and BeMicro-SDK boards would also have enough logic.

What is just as important, is what are your I/O requirements? Does your PID controller need an ADC or a DAC? How are you going to interface to the real-world?

You need to look at both the FPGA board and the interface boards, and make sure you can connect them together without too much work.

The DE2-70 and DE0-nano interface to boards via their GPIO headers. Terasic have some ADC/DAC boards.

The BeMicro and BeMicro-SDK boards have an 80-pin edge connector. You can connect a PROTO board to that header for interfacing to custom logic.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
The DE2-70 has plenty of logic for a PID controller. The lower-cost DE0-nano, BeMicro, and BeMicro-SDK boards would also have enough logic.
--- Quote End ---

I absolutely agree. I can tell, that I have implemented a power electronics controller with multiple PIDs on a small (8K LEs) Cyclone II, DE0 Nano has factor 2.5 more.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I absolutely agree. I can tell, that I have implemented a power electronics controller with multiple PIDs on a small (8K LEs) Cyclone II, DE0 Nano has factor 2.5 more.
--- Quote End ---

How about the Max7000 ,I got one free . is it plenty of logic for a PID controller???

If not i have to bye another board.

Gazal
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
How about the Max7000 ,I got one free . is it plenty of logic for a PID controller?
--- Quote End ---

Not at all. MAX7000 is a CPLD, a reasonable solution for pure digital logic designs. Even the largest MAX7000 with 512 macro cells won't allow more than a rudimentary (e.g. 8 bit data width) controller. A recent development kit like DE-0 Nano would make much more sense.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Not at all. MAX7000 is a CPLD, a reasonable solution for pure digital logic designs. Even the largest MAX7000 with 512 macro cells won't allow more than a rudimentary (e.g. 8 bit data width) controller. A recent development kit like DE-0 Nano would make much more sense.
--- Quote End ---

well, i am not working on a conventional PID, so i'm a little bit worry if the Nano will be plenty to apply an intelligent algorithms.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
i am not working on a conventional PID, so i'm a little bit worry if the Nano will be plenty to apply an intelligent algorithms.
--- Quote End ---

So implement your algorithm and synthesize it in a device.

You do not need a board for this. Just select the same device as used on the DE0-nano and see if it has enough resources. If it does not, then try a larger device, or try a larger device from a specific evaluation board, eg., the DE2-115.

Cheers,
Dave

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Implementation of Digital PID controller in FPGA

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