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Altera_Forum
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17 years ago

Implementation of Digital PID controller in FPGA

I'm trying to implement a PI controller in FPGA using schematic entry method in altera quartus II . I'm using the following equivalent PI controller equation, c(n) = c(n-1)+kp*(e(n)-e(n-1))+Ki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Not at all. MAX7000 is a CPLD, a reasonable solution for pure digital logic designs. Even the largest MAX7000 with 512 macro cells won't allow more than a rudimentary (e.g. 8 bit data width) controller. A recent development kit like DE-0 Nano would make much more sense.

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well, i am not working on a conventional PID, so i'm a little bit worry if the Nano will be plenty to apply an intelligent algorithms.