FPGA to HPS Communication wth External Avalon

Hi Friends,

I have the Terasic DeE-0 Nano Development board with Cyclone V and ARM Cortex HPS. As a part of my project, I have send some huge amount of data ( in megabytes ) from FPGA to HPS and store it in the SDcard in the HPS system whichis running Linux on it.

I have used the HPS Component and "External Bus to Avalon Bridge" to connect from FPGA Fabric to SDRAM, so that I can send the data through the exported external interface. Now, the problem is I am getting an error with memory range. The screenshot is attached.

These are the Qsys messages and the first line is the error message.

Error: FPGA2SDRAMAVEXBRIDGE.HPS_SDRAM.avalon_master: HPS_Host.f2h_sdram0_data (0x0..0xffffffff) is outside the master's address range (0x0..0x3fffffff)
Warning: FPGA2SDRAMAVEXBRIDGE.HPS_Host: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
Warning: FPGA2SDRAMAVEXBRIDGE.HPS_Host: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
Warning: FPGA2SDRAMAVEXBRIDGE.HPS_Host: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
Warning: FPGA2SDRAMAVEXBRIDGE.HPS_Host: set_interface_assignment: Interface "hps_io" does not exist
Info: FPGA2SDRAMAVEXBRIDGE.HPS_Host: HPS Main PLL counter settings: n = 0  m = 73
Info: FPGA2SDRAMAVEXBRIDGE.HPS_Host: HPS peripherial PLL counter settings: n = 0  m = 39

This is the problem. Does somebody have an idea how to resolve it ?. Or if can suggest me some other way it would be greatly appreciated.

I am parallelelly trying a DMA , but the above solution would be more convenient for me.