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Altera_Forum
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10 years ago

FPGA to HPS Communication wth External Avalon

Hi Friends, I have the Terasic DeE-0 Nano Development board with Cyclone V and ARM Cortex HPS. As a part of my project, I have send some huge amount of data ( in megabytes ) from FPGA to HPS and...
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Altera_Forum
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10 years ago

Hi,

From following ( http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=941&partno=2 ), I came to know that board which you are using has 1 GB DDR3 SDRAM memory. Now, to represent this memory, we do not need 32 bit address width. ( It's data bus is of 32 bits.) I just want you to see how you have selected Address width for your f2g_sdram_data. Is it really configured for 1GB memory or something else?

Kind Regards,

Bhaumik