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Altera_Forum
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10 years ago

FPGA to HPS Communication wth External Avalon

Hi Friends, I have the Terasic DeE-0 Nano Development board with Cyclone V and ARM Cortex HPS. As a part of my project, I have send some huge amount of data ( in megabytes ) from FPGA to HPS and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hello,

Yes, the the f2h_sdram_data is the Avalon slave. I connected the Avalon_master of the bridge to this slave port. I am able to connect, but only problem is the memory mismatch.

Could you please tell what do you mean by "Does it really need 32 bit address width" ?

Do you mean the slave requires the 32 bit address width ? if so, no the maximum can be configured is 29 bits.

But even though, how will I connect these two ports. Is there any documents tutorials for this ? I could not find anything which shows Qsys configuration,unfortunately.

Best Regards.