Altera_Forum
Honored Contributor
12 years agoDM9000A problem with sending packets
Hi guys, I have a problem with my DM9000A project. My project is sending packets from FPGA to PC using only VHDL codes to program. Some parts I copied from internet. Then I used wireshark to calculate sending packets rate but it showed some error. Instead of sending UDP packets from FPGA to PC it does in reverse way. I dont know what's wrong with my code :( Below is my project, target MAC, IP and own MAC, IP are my PC and kit, respectively. Plz help me. Sorry for my bad english :)
https://www.dropbox.com/s/ssmigqkoqczchwd/dm9000a.rar