DE2-70 / TRDB-D5M / TRDB-LTM VHDL reference designs?

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As a VHDL programmer with no Verilog experience these reference designs may as well be written in Swahili and translated into ancient Sumerian!

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To my opinion, the languages aren't so different at all. Most VHDL constructs have a direct Verilog correspondence. The real bad thing with the said example design is the lack of any meaningful comments, excect for a copyright notice.

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To my opinion, the languages aren't so different at all. Most VHDL constructs have a direct Verilog correspondence. The real bad thing with the said example design is the lack of any meaningful comments, excect for a copyright notice.

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I have to laugh everyone that writes in verilog says exactly that ... "The languages are not that different". But I have seen no one actually translate anything and BELIEVE me there is a boat load of difference between them! I have pretty much given up trying to translate and will spend the summer learning verilog so I can just write in whatever language I get my reference designs in.

I expressed just my private opinion. I'm preferring VHDL, but also have been asked by a customer to contribute to a project maintained in Verilog. Apart from this, Altera IP is utilizing both languages, often mixed in a project. You need to handle both to understand it. This has been the case e.g. with the MAX II PFL controller reference design, I adapted it for a multiple FPGA enviroment.

I basically keep my opinion, that there is a rather close correspondence between Verilog and VHDL language constructs. I admit, that some Verilog syntax elements look confusing to a pure VHDL programmer, but you should be able to understand their meaning within a few hours. Some elements, that have been inherited from the C programming language should be known to an engineer anyway.

i was wondering if anyone managed to implement the ltm and d5m into the nios enviroment?

can anyone tell me if the sopc has built in drivers for the ltm and d5m, or would i have to develope the drivers myself..

thanks a bunch

i'm not sure regarding d5m, but i currently attempt to connect the ltm module to nios with partial success.

i will update on my progress.

Hi,

we want to buy this platform.

their application used the USB type b connection What do you think about the document provide to understand the link between(ISP1362, FPGA , USB), the tutorials on this part have been provided or not?

i plane to realize the Image Fusion of 2 Video Sensors with Board DE2-70. which Software,hardware and IP Core can i use to do that and what about their licensing?

Thanks

could you please share your vhdl code for interfacing the camera to the DE2 board or similar.

Please help me

could you please share your vhdl code for interfacing the camera to the DE2 board or similar.

Please help me

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DE2-70 : 70,000 LUT version of DE2

TRDB-D5M - 5Mpixel camera component for DE2/DE2-70 from Terasic

TRDB-LTM - 4.3" 800 x 480 res touch screen for DE2/DE2-70

The camera and touch screen come with some nice reference designs for the DE2-70 and there are other designs on clares DE2-70 dev website. Unfortunately the designs that ship with the camera and touch screen are all written in Verilog and don't have a lick of documentation! The ones on Clare's site have some documentation but have to be translated and the code is still all in Verilog.

As a VHDL programmer with no Verilog experience these reference designs may as well be written in Swahili and translated into ancient Sumerian!

In other words they are completed useless to me. Has anyone written any kind of reference designs in VHDL to interface to the DE2-70, TRDB-D5M, and TRDB-LTM?

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I saw in the post:

you were able to interface DE2 with TRDB_D5M and TRDB_LTM

could you please share your vhdl code for interfacing the camera to the DE2 board or similar. I'm willing to pay you if its helpful.

Please help me

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I expressed just my private opinion. I'm preferring VHDL, but also have been asked by a customer to contribute to a project maintained in Verilog. Apart from this, Altera IP is utilizing both languages, often mixed in a project. You need to handle both to understand it. This has been the case e.g. with the MAX II PFL controller reference design, I adapted it for a multiple FPGA enviroment.

I basically keep my opinion, that there is a rather close correspondence between Verilog and VHDL language constructs. I admit, that some Verilog syntax elements look confusing to a pure VHDL programmer, but you should be able to understand their meaning within a few hours. Some elements, that have been inherited from the C programming language should be known to an engineer anyway.

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