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To my opinion, the languages aren't so different at all. Most VHDL constructs have a direct Verilog correspondence. The real bad thing with the said example design is the lack of any meaningful comments, excect for a copyright notice.
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I have to laugh everyone that writes in verilog says exactly that ... "The languages are not that different". But I have seen no one actually translate anything and BELIEVE me there is a boat load of difference between them! I have pretty much given up trying to translate and will spend the summer learning verilog so I can just write in whatever language I get my reference designs in.
Honored Contributor
