DE2-70 / TRDB-D5M / TRDB-LTM VHDL reference designs?

I saw in the post:

you were able to interface DE2 with TRDB_D5M and TRDB_LTM

could you please share your vhdl code for interfacing the camera to the DE2 board or similar. I'm willing to pay you if its helpful.

Please help me

--- Quote Start ---

I expressed just my private opinion. I'm preferring VHDL, but also have been asked by a customer to contribute to a project maintained in Verilog. Apart from this, Altera IP is utilizing both languages, often mixed in a project. You need to handle both to understand it. This has been the case e.g. with the MAX II PFL controller reference design, I adapted it for a multiple FPGA enviroment.

I basically keep my opinion, that there is a rather close correspondence between Verilog and VHDL language constructs. I admit, that some Verilog syntax elements look confusing to a pure VHDL programmer, but you should be able to understand their meaning within a few hours. Some elements, that have been inherited from the C programming language should be known to an engineer anyway.

--- Quote End ---