Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- As a VHDL programmer with no Verilog experience these reference designs may as well be written in Swahili and translated into ancient Sumerian! --- Quote End --- To my opinion, the languages aren't so different at all. Most VHDL constructs have a direct Verilog correspondence. The real bad thing with the said example design is the lack of any meaningful comments, excect for a copyright notice.