Use the adder on cyclone V FPGA board

Hello,

I am working on implementing a TDC using the Cyclone V FPGA board and I have referred to some papers that suggest using two adders in the LUT to construct a carry chain. Therefore, I have been trying to write a Verilog code that allows my FPGA to generate a carry chain composed of adders.

However, I have tried various adder implementations, including build a full adders with gate level and calling various adders from the IP catalog, but they are easily optimized into hardware structures composed of look-up tables during fitter operation. This makes it difficult for me to implement my TDC paper.

I would like to ask if there is any way to directly use the adder in LAB. I have read the Designing with Low-Level Primitives datasheet provided by Intel (attached), but this datasheet does not mention any low-level primitives related to adders. Therefore, I would like to inquire where I can obtain important information.

 

Additionally, I am aware that other delay elements can be used, but I want to use adders to construct my TDC because other delay elements have a minimum delay time of around 300ps, while using adders as delay elements results in a delay time of approximately 20ps, which is significantly different from other delay elements.

I would greatly appreciate it if you could help me solve this problem. Thank you!