Forum Discussion
kgrcfff
New Contributor
New ContributorUse the adder on cyclone V FPGA board
Hello,
I am working on implementing a TDC using the Cyclone V FPGA board and I have referred to some papers that suggest using two adders in the LUT to construct a carry chain. Therefore, I ha...
Nurina
Regular Contributor
Regular ContributorHello,
What is TDC? Time to digital converter? Is this something you are trying to design?
I would suggest to write a Verilog code for the carry chain composed of adders and use these settings:
- Carry Chain Length logic option: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/logicops/logicops/def_carry_chain_length.htm
- Try preserve signals: https://www.intel.com/content/www/us/en/docs/programmable/683236/21-4/preserving-signals-for-monitoring-and.html
If these doesn't help, could you share your code so I can try from my end?
Thanks,
Nurina
