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kgrcfff's avatar
kgrcfff
Icon for New Contributor rankNew Contributor
3 years ago

Use the adder on cyclone V FPGA board

Hello, I am working on implementing a TDC using the Cyclone V FPGA board and I have referred to some papers that suggest using two adders in the LUT to construct a carry chain. Therefore, I ha...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


What is TDC? Time to digital converter? Is this something you are trying to design?

I would suggest to write a Verilog code for the carry chain composed of adders and use these settings:


If these doesn't help, could you share your code so I can try from my end?


Thanks,

Nurina