TSE -> SGDMA -> SOC(through f2sdram)

Hi,

I'm trying to transfer an old design with multiple TSEs / SGMDAs and a NIOS to a newer Agilex 5.
We are also evaluating the use of the SOC instead of the NIOS in the design.
I've made a minimized platform design for it but it fails during synthesis with the notorious error for the f2sdram bus:

There is both a 'memory -> streaming' and 'streaming -> memory' sgdma in the design present, so both read and write port on the axi bus should be present.
If I connect the SGDMA's to the fpga2hps bus the same error is generated.

Are there settings in the SGDMAs that needs to be set to a certain value so that the correct read/write avalon MM/AXI interface is generated?