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ohfpga1's avatar
ohfpga1
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13 days ago

Timings eMMC

Hi, latest datasheet of SoC « 813918/2026.01.05 » lists in paragraph « HPS SD/eMMC Timing Characteristics » the constraints of eMMC, applicable to memory component but does not define any timing dat...
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KianHinT_altera's avatar
KianHinT_altera
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2 hours ago

Hi ohfpga1 

 

Could you refer to the Agilex 5 datasheet under SD/EMMC timing characteristics (https://docs.altera.com/r/docs/813918/current/agilextm-5-fpgas-and-socs-device-data-sheet/agilextm-5-fpgas-and-socs-device-data-sheet)

 

 

Example for legacy, HS_SDR

 

There is also timing tables for the rest of the modes eg (HS,HS200, HS400). Could you refer to the document and see whether it addresses your timing question?

 

Thanks

Regards

Kian