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Amoon's avatar
Amoon
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5 months ago

Sopc2DTS with Agilex 7

After generating a qsys_top.sopcinfo with quartus for the SocFPGA Agilex 7 design, i'm trying to get the .dts then the .dtb from it via sopc2dts. I'm encountring the following issue:

$ java -jar sopc2dts.jar --input ../Bureau/qsys_top.sopcinfo --output essai_libs.dts --type dts --extra-component-libs sopc_components_altera.xml --extra-component-libs sopc_components_fps.xml --extra-component-libs sopc_components_labx.xml --extra-component-libs sopc_components_others.xml


Unsupported interface kind: ftile_hssi_system_clock_source
Unsupported interface kind: ftile_hssi_reference_clock_source
Unsupported interface kind: ftile_hssi_reference_clock_sink
Unsupported interface kind: ftile_hssi_reference_clock_sink
Unsupported interface kind: ftile_hssi_reference_clock_sink
Unsupported interface kind: ftile_hssi_reference_clock_sink
Unsupported interface kind: ftile_hssi_reference_clock_sink
Unsupported interface kind: ftile_hssi_reference_clock_sink
Unsupported interface kind: ftile_hssi_reference_clock_sink
Unsupported interface kind: ftile_hssi_reference_clock_sink
Unsupported interface kind: ftile_hssi_system_clock_sink
...
Unsupported interface kind: ftile_hssi_system_clock_source
Unsupported interface kind: ftile_hssi_reference_clock_source
Component agilex_hps of class intel_agilex_hps is unknown
Component emif_cal_0 of class altera_emif_cal is unknown
Component emif_cal_1 of class altera_emif_cal is unknown
Component emif_fpga of class altera_emif_fm is unknown
Component emif_fpga_1 of class altera_emif_fm is unknown
Component emif_hps of class altera_emif_fm_hps is unknown
Component mm_ccb_0 of class mm_ccb is unknown
Component mm_ccb_1 of class mm_ccb is unknown
Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown
Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown
Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown
Component agilex_hps of class intel_agilex_hps is unknown
Component emif_cal_0 of class altera_emif_cal is unknown
Component emif_cal_1 of class altera_emif_cal is unknown
Component emif_fpga of class altera_emif_fm is unknown
Component emif_fpga_1 of class altera_emif_fm is unknown
Component emif_hps of class altera_emif_fm_hps is unknown
Component mm_ccb_0 of class mm_ccb is unknown
Component mm_ccb_1 of class mm_ccb is unknown
Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown
Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown
Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown
Component agilex_hps of class intel_agilex_hps is unknown
Component emif_cal_0 of class altera_emif_cal is unknown
Component emif_cal_1 of class altera_emif_cal is unknown
Component emif_fpga of class altera_emif_fm is unknown
Component emif_fpga_1 of class altera_emif_fm is unknown
Component emif_hps of class altera_emif_fm_hps is unknown
Component mm_ccb_0 of class mm_ccb is unknown
Component mm_ccb_1 of class mm_ccb is unknown
Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown
Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown
Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown
Component xcvr_12a_bank_systemclk_f_0 of class systemclk_f is unknown
Component xcvr_12a_bank_xcvr_12a_fmc_quad2 of class directphy_f is unknown
Component xcvr_12a_bank_xcvr_12a_fmc_quad3 of class directphy_f is unknown
Component xcvr_12a_bank_xcvr_12a_qsfp of class directphy_f is unknown
Component xcvr_13a_qsys_fmc of class directphy_f is unknown
Component xcvr_13a_qsys_qsfp1 of class directphy_f is unknown
Component xcvr_13a_qsys_systemclk_f_0 of class systemclk_f is unknown
Component xcvr_13c_qsys_fmc of class directphy_f is unknown
Component xcvr_13c_qsys_systemclk_f_0 of class systemclk_f is unknown
Unable to find a master of type CPU. Randomly selecting the first master we find (agilex_hps).

How to fix this and have a complete and correct device tree that can be compiled into .dtb?
I'm working with agilex 7.

+
if i wanna custom an OS and do it in the HPS of my board (like adding new modules using gpios), is it mandatory to add some blocks in the .dts ?

Sw Library

6 Replies

  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    4 months ago

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


  • ShoH_Altera's avatar
    ShoH_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hi @Amoon ,

    Thanks for your additional inputs.
    So, May I assume that you want to know how to write a kernel module that handles input signals on GPIO pins as interrupts?

    Which GPIO pins are you targeting, FPGA pins or HPS dedicated GPIO pins?


    • Amoon's avatar
      Amoon
      Icon for New Contributor rankNew Contributor
      5 months ago

      hi @ShoH_Altera

      Thanks for your message.

      Yes, indeed — I am developing a kernel module that handles input signals via GPIO interrupts, primarily to simulate or test time event (TE) mechanisms. The goal is to receive rising/falling edge events on GPIO and synchronize actions accordingly.

      Currently, I am targeting HPS-dedicated GPIOs on the Agilex 7 SoC.

      This choice is based on the assumption that these pins are directly controllable and better integrated with the HPS interrupt controller.

      However, I remain open to later extending the support to FPGA-assigned GPIOs (via the GPIO bridge), once the system is stable and the correct mapping (.dts) is validated.

      • ShoH_Altera's avatar
        ShoH_Altera
        Icon for Occasional Contributor rankOccasional Contributor
        5 months ago

        Hi @Amoon ,

        Device Tree for HPS GPIO:

        In Agilex 7 HPS, the SynopsysDesignWare APB General Purpose Programming I/O (DW_apb_gpio) peripheral is used as the GPIO controller hardware, stated in Agilex 7 HPS Technical Reference Manual(TRM). So, we can use the Synopsys DesignWare APB GPIO driver for the GPIO controller.

        drivers/gpio/gpio-dwapb.c

        See this Doc file in the kernel source for information on how to write the device tree information for this device driver.

        Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml

        But there's no need to worry too much. All definitions required to use the Agilex7 HPS GPIO HW, including interrupt request functionality, are provided/contained in this .dtsi file.

        arch/arm64/boot/dts/intel/socfpga_agilex.dtsi

        All you need to do in your device tree file is include the .dtsi file and add enable statements for the gpio node(s) you want to use, like in this example:

        arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts

        In the above .dts file, the GPIO1 node is enabed, which means that the 24 IO lines connected to the GPIO1 interface are enabled.

        &gpio1 {
         status = "okay";
        };

        You can enable the GPIO0 by by adding the same description for "&gpio0".

        That's about the device tree. Please let me know if there is anything still unclear.

        How to develop a kernel module using the GPIO driver:

        Now, you can use the standard GPIO driver APIs documented in the kernel documentation for your kernel module. For example, for v6.12 kernel:

        https://www.kernel.org/doc/html/v6.12/driver-api/gpio/index.html#

        Regarding your questions, I think you will find your solutions by referring to the sections.

        > 1.How to associate my module with the specific GPIO pin that generates the interrupt.

        https://www.kernel.org/doc/html/v6.12/driver-api/gpio/consumer.html#obtaining-and-disposing-gpios

        > 2. How to identify which GPIO pin is responsible for a particular interrupt event

        https://www.kernel.org/doc/html/v6.12/driver-api/gpio/consumer.html#using-gpios

        If you still have difficulties developing your kernel modules, please post.

        Thanks!

  • ShoH_Altera's avatar
    ShoH_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    5 months ago

    Hi @Amoon ,

    The device tree generator tool(sopc2dts) is a very old tool and supports only the Linux kernel version targeted by the associated v18.0 or earlier GSRD. And the tool supports only Cyclone V, Arria V and Arria 10 HPS devices, not Agilex 7.

    It is recommended to manage the Device Tree manually by using the Device Tree files provided by the kernel as a baseline, and by adding the FPGA IP and board information manually. Just like a normal Linux development flow.

    If you are new to device tree, I'd to read this article once:

    https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/Investigating-Device-Trees/td-p/1610544

    Regarding this question:

    > is it mandatory to add some blocks in the .dts ?

    It depends on what kernel driver you use in your design. Which hardware modules do you want to add? Maybe I can help you write the device tree node you should add.

    Thanks,

    • Amoon's avatar
      Amoon
      Icon for New Contributor rankNew Contributor
      5 months ago

      Hi @ShoH_Altera ,

      Thanks for your help.

      I'm customizing a Linux kernel module to handle specific ticks or interrupts triggered by a particular GPIO pin.
      What I need to understand is:

      1. How to associate my module with the specific GPIO pin that generates the interrupt.

      2. How to identify which GPIO pin is responsible for a particular interrupt event — in this case, it's a time event interrupt.