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Re: Sopc2DTS with Agilex 7
hi @ShoH_Altera Thanks for your message. Yes, indeed — I am developing a kernel module that handles input signals via GPIO interrupts, primarily to simulate or test time event (TE) mechanisms. The goal is to receive rising/falling edge events on GPIO and synchronize actions accordingly. Currently, I am targeting HPS-dedicated GPIOs on the Agilex 7 SoC. This choice is based on the assumption that these pins are directly controllable and better integrated with the HPS interrupt controller. However, I remain open to later extending the support to FPGA-assigned GPIOs (via the GPIO bridge), once the system is stable and the correct mapping (.dts) is validated.1.9KViews0likes1CommentRe: Sopc2DTS with Agilex 7
Hi @ShoH_Altera , Thanks for your help. I'm customizing a Linux kernel module to handle specific ticks or interrupts triggered by a particular GPIO pin. What I need to understand is: How to associate my module with the specific GPIO pin that generates the interrupt. How to identify which GPIO pin is responsible for a particular interrupt event — in this case, it's a time event interrupt.2.2KViews0likes0CommentsSopc2DTS with Agilex 7
After generating a qsys_top.sopcinfo with quartus for the SocFPGA Agilex 7 design, i'm trying to get the .dts then the .dtb from it via sopc2dts. I'm encountring the following issue: $ java -jar sopc2dts.jar --input ../Bureau/qsys_top.sopcinfo --output essai_libs.dts --type dts --extra-component-libs sopc_components_altera.xml --extra-component-libs sopc_components_fps.xml --extra-component-libs sopc_components_labx.xml --extra-component-libs sopc_components_others.xml Unsupported interface kind: ftile_hssi_system_clock_source Unsupported interface kind: ftile_hssi_reference_clock_source Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_system_clock_sink ... Unsupported interface kind: ftile_hssi_system_clock_source Unsupported interface kind: ftile_hssi_reference_clock_source Component agilex_hps of class intel_agilex_hps is unknown Component emif_cal_0 of class altera_emif_cal is unknown Component emif_cal_1 of class altera_emif_cal is unknown Component emif_fpga of class altera_emif_fm is unknown Component emif_fpga_1 of class altera_emif_fm is unknown Component emif_hps of class altera_emif_fm_hps is unknown Component mm_ccb_0 of class mm_ccb is unknown Component mm_ccb_1 of class mm_ccb is unknown Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown Component agilex_hps of class intel_agilex_hps is unknown Component emif_cal_0 of class altera_emif_cal is unknown Component emif_cal_1 of class altera_emif_cal is unknown Component emif_fpga of class altera_emif_fm is unknown Component emif_fpga_1 of class altera_emif_fm is unknown Component emif_hps of class altera_emif_fm_hps is unknown Component mm_ccb_0 of class mm_ccb is unknown Component mm_ccb_1 of class mm_ccb is unknown Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown Component agilex_hps of class intel_agilex_hps is unknown Component emif_cal_0 of class altera_emif_cal is unknown Component emif_cal_1 of class altera_emif_cal is unknown Component emif_fpga of class altera_emif_fm is unknown Component emif_fpga_1 of class altera_emif_fm is unknown Component emif_hps of class altera_emif_fm_hps is unknown Component mm_ccb_0 of class mm_ccb is unknown Component mm_ccb_1 of class mm_ccb is unknown Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown Component xcvr_12a_bank_systemclk_f_0 of class systemclk_f is unknown Component xcvr_12a_bank_xcvr_12a_fmc_quad2 of class directphy_f is unknown Component xcvr_12a_bank_xcvr_12a_fmc_quad3 of class directphy_f is unknown Component xcvr_12a_bank_xcvr_12a_qsfp of class directphy_f is unknown Component xcvr_13a_qsys_fmc of class directphy_f is unknown Component xcvr_13a_qsys_qsfp1 of class directphy_f is unknown Component xcvr_13a_qsys_systemclk_f_0 of class systemclk_f is unknown Component xcvr_13c_qsys_fmc of class directphy_f is unknown Component xcvr_13c_qsys_systemclk_f_0 of class systemclk_f is unknown Unable to find a master of type CPU. Randomly selecting the first master we find (agilex_hps). How to fix this and have a complete and correct device tree that can be compiled into .dtb? I'm working with agilex 7. + if i wanna custom an OS and do it in the HPS of my board (like adding new modules using gpios), is it mandatory to add some blocks in the .dts ?2.6KViews0likes6Comments